| Nordic Thingy:52 v2.0.0

drv_sx1509_bitfields.h
1 /*
2 Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 1. Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10
11 2. Redistributions in binary form, except as embedded into a Nordic
12 Semiconductor ASA integrated circuit in a product or a software update for
13 such product, must reproduce the above copyright notice, this list of
14 conditions and the following disclaimer in the documentation and/or other
15 materials provided with the distribution.
16
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18 contributors may be used to endorse or promote products derived from this
19 software without specific prior written permission.
20
21 4. This software, with or without modification, must only be used with a
22 Nordic Semiconductor ASA integrated circuit.
23
24 5. Any software provided in binary form under this license must not be reverse
25 engineered, decompiled, modified and/or disassembled.
26
27 THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
28 OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
31 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
33 GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef DRV_SX1509_BITFIELDS_H__
40 #define DRV_SX1509_BITFIELDS_H__
41
42 #define DRV_SX1509_FADE_SUPPORTED_PORT_MASK (0xF0F0)
43
44 /* Register: INPBUFDISABLE. */
45 /* Description: Input buffer disable register. */
46
47
48 /* Field INPBUF15: Disables/Enables the input buffer of the I/O pin. */
49 #define DRV_SX1509_INPBUFDISABLE_INPBUF15_Pos (15)
50 #define DRV_SX1509_INPBUFDISABLE_INPBUF15_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF15_Pos)
51 #define DRV_SX1509_INPBUFDISABLE_INPBUF15_Disabled (0)
52 #define DRV_SX1509_INPBUFDISABLE_INPBUF15_Enabled (1)
55 /* Field INPBUF14: Disables/Enables the input buffer of the I/O pin. */
56 #define DRV_SX1509_INPBUFDISABLE_INPBUF14_Pos (14)
57 #define DRV_SX1509_INPBUFDISABLE_INPBUF14_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF14_Pos)
58 #define DRV_SX1509_INPBUFDISABLE_INPBUF14_Disabled (0)
59 #define DRV_SX1509_INPBUFDISABLE_INPBUF14_Enabled (1)
62 /* Field INPBUF13: Disables/Enables the input buffer of the I/O pin. */
63 #define DRV_SX1509_INPBUFDISABLE_INPBUF13_Pos (13)
64 #define DRV_SX1509_INPBUFDISABLE_INPBUF13_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF13_Pos)
65 #define DRV_SX1509_INPBUFDISABLE_INPBUF13_Disabled (0)
66 #define DRV_SX1509_INPBUFDISABLE_INPBUF13_Enabled (1)
69 /* Field INPBUF12: Disables/Enables the input buffer of the I/O pin. */
70 #define DRV_SX1509_INPBUFDISABLE_INPBUF12_Pos (12)
71 #define DRV_SX1509_INPBUFDISABLE_INPBUF12_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF12_Pos)
72 #define DRV_SX1509_INPBUFDISABLE_INPBUF12_Disabled (0)
73 #define DRV_SX1509_INPBUFDISABLE_INPBUF12_Enabled (1)
76 /* Field INPBUF11: Disables/Enables the input buffer of the I/O pin. */
77 #define DRV_SX1509_INPBUFDISABLE_INPBUF11_Pos (11)
78 #define DRV_SX1509_INPBUFDISABLE_INPBUF11_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF11_Pos)
79 #define DRV_SX1509_INPBUFDISABLE_INPBUF11_Disabled (0)
80 #define DRV_SX1509_INPBUFDISABLE_INPBUF11_Enabled (1)
83 /* Field INPBUF10: Disables/Enables the input buffer of the I/O pin. */
84 #define DRV_SX1509_INPBUFDISABLE_INPBUF10_Pos (10)
85 #define DRV_SX1509_INPBUFDISABLE_INPBUF10_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF10_Pos)
86 #define DRV_SX1509_INPBUFDISABLE_INPBUF10_Disabled (0)
87 #define DRV_SX1509_INPBUFDISABLE_INPBUF10_Enabled (1)
90 /* Field INPBUF9: Disables/Enables the input buffer of the I/O pin. */
91 #define DRV_SX1509_INPBUFDISABLE_INPBUF9_Pos (9)
92 #define DRV_SX1509_INPBUFDISABLE_INPBUF9_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF9_Pos)
93 #define DRV_SX1509_INPBUFDISABLE_INPBUF9_Disabled (0)
94 #define DRV_SX1509_INPBUFDISABLE_INPBUF9_Enabled (1)
97 /* Field INPBUF8: Disables/Enables the input buffer of the I/O pin. */
98 #define DRV_SX1509_INPBUFDISABLE_INPBUF8_Pos (8)
99 #define DRV_SX1509_INPBUFDISABLE_INPBUF8_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF8_Pos)
100 #define DRV_SX1509_INPBUFDISABLE_INPBUF8_Disabled (0)
101 #define DRV_SX1509_INPBUFDISABLE_INPBUF8_Enabled (1)
104 /* Field INPBUF7: Disables/Enables the input buffer of the I/O pin. */
105 #define DRV_SX1509_INPBUFDISABLE_INPBUF7_Pos (7)
106 #define DRV_SX1509_INPBUFDISABLE_INPBUF7_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF7_Pos)
107 #define DRV_SX1509_INPBUFDISABLE_INPBUF7_Disabled (0)
108 #define DRV_SX1509_INPBUFDISABLE_INPBUF7_Enabled (1)
111 /* Field INPBUF6: Disables/Enables the input buffer of the I/O pin. */
112 #define DRV_SX1509_INPBUFDISABLE_INPBUF6_Pos (6)
113 #define DRV_SX1509_INPBUFDISABLE_INPBUF6_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF6_Pos)
114 #define DRV_SX1509_INPBUFDISABLE_INPBUF6_Disabled (0)
115 #define DRV_SX1509_INPBUFDISABLE_INPBUF6_Enabled (1)
118 /* Field INPBUF5: Disables/Enables the input buffer of the I/O pin. */
119 #define DRV_SX1509_INPBUFDISABLE_INPBUF5_Pos (5)
120 #define DRV_SX1509_INPBUFDISABLE_INPBUF5_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF5_Pos)
121 #define DRV_SX1509_INPBUFDISABLE_INPBUF5_Disabled (0)
122 #define DRV_SX1509_INPBUFDISABLE_INPBUF5_Enabled (1)
125 /* Field INPBUF4: Disables/Enables the input buffer of the I/O pin. */
126 #define DRV_SX1509_INPBUFDISABLE_INPBUF4_Pos (4)
127 #define DRV_SX1509_INPBUFDISABLE_INPBUF4_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF4_Pos)
128 #define DRV_SX1509_INPBUFDISABLE_INPBUF4_Disabled (0)
129 #define DRV_SX1509_INPBUFDISABLE_INPBUF4_Enabled (1)
132 /* Field INPBUF3: Disables/Enables the input buffer of the I/O pin. */
133 #define DRV_SX1509_INPBUFDISABLE_INPBUF3_Pos (3)
134 #define DRV_SX1509_INPBUFDISABLE_INPBUF3_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF3_Pos)
135 #define DRV_SX1509_INPBUFDISABLE_INPBUF3_Disabled (0)
136 #define DRV_SX1509_INPBUFDISABLE_INPBUF3_Enabled (1)
139 /* Field INPBUF2: Disables/Enables the input buffer of the I/O pin. */
140 #define DRV_SX1509_INPBUFDISABLE_INPBUF2_Pos (2)
141 #define DRV_SX1509_INPBUFDISABLE_INPBUF2_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF2_Pos)
142 #define DRV_SX1509_INPBUFDISABLE_INPBUF2_Disabled (0)
143 #define DRV_SX1509_INPBUFDISABLE_INPBUF2_Enabled (1)
146 /* Field INPBUF1: Disables/Enables the input buffer of the I/O pin. */
147 #define DRV_SX1509_INPBUFDISABLE_INPBUF1_Pos (1)
148 #define DRV_SX1509_INPBUFDISABLE_INPBUF1_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF1_Pos)
149 #define DRV_SX1509_INPBUFDISABLE_INPBUF1_Disabled (0)
150 #define DRV_SX1509_INPBUFDISABLE_INPBUF1_Enabled (1)
153 /* Field INPBUF0: Disables/Enables the input buffer of the I/O pin. */
154 #define DRV_SX1509_INPBUFDISABLE_INPBUF0_Pos (0)
155 #define DRV_SX1509_INPBUFDISABLE_INPBUF0_Msk (0x1 << DRV_SX1509_INPBUFDISABLE_INPBUF0_Pos)
156 #define DRV_SX1509_INPBUFDISABLE_INPBUF0_Disabled (0)
157 #define DRV_SX1509_INPBUFDISABLE_INPBUF0_Enabled (1)
160 /* Register: LONGSLEWRATE. */
161 /* Description: Output buffer long slew register. */
162
163
164 /* Field PIN15: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
165 #define DRV_SX1509_LONGSLEWRATE_PIN15_Pos (15)
166 #define DRV_SX1509_LONGSLEWRATE_PIN15_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN15_Pos)
167 #define DRV_SX1509_LONGSLEWRATE_PIN15_Disabled (0)
168 #define DRV_SX1509_LONGSLEWRATE_PIN15_Enabled (1)
171 /* Field PIN14: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
172 #define DRV_SX1509_LONGSLEWRATE_PIN14_Pos (14)
173 #define DRV_SX1509_LONGSLEWRATE_PIN14_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN14_Pos)
174 #define DRV_SX1509_LONGSLEWRATE_PIN14_Disabled (0)
175 #define DRV_SX1509_LONGSLEWRATE_PIN14_Enabled (1)
178 /* Field PIN13: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
179 #define DRV_SX1509_LONGSLEWRATE_PIN13_Pos (13)
180 #define DRV_SX1509_LONGSLEWRATE_PIN13_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN13_Pos)
181 #define DRV_SX1509_LONGSLEWRATE_PIN13_Disabled (0)
182 #define DRV_SX1509_LONGSLEWRATE_PIN13_Enabled (1)
185 /* Field PIN12: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
186 #define DRV_SX1509_LONGSLEWRATE_PIN12_Pos (12)
187 #define DRV_SX1509_LONGSLEWRATE_PIN12_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN12_Pos)
188 #define DRV_SX1509_LONGSLEWRATE_PIN12_Disabled (0)
189 #define DRV_SX1509_LONGSLEWRATE_PIN12_Enabled (1)
192 /* Field PIN11: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
193 #define DRV_SX1509_LONGSLEWRATE_PIN11_Pos (11)
194 #define DRV_SX1509_LONGSLEWRATE_PIN11_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN11_Pos)
195 #define DRV_SX1509_LONGSLEWRATE_PIN11_Disabled (0)
196 #define DRV_SX1509_LONGSLEWRATE_PIN11_Enabled (1)
199 /* Field PIN10: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
200 #define DRV_SX1509_LONGSLEWRATE_PIN10_Pos (10)
201 #define DRV_SX1509_LONGSLEWRATE_PIN10_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN10_Pos)
202 #define DRV_SX1509_LONGSLEWRATE_PIN10_Disabled (0)
203 #define DRV_SX1509_LONGSLEWRATE_PIN10_Enabled (1)
206 /* Field PIN9: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
207 #define DRV_SX1509_LONGSLEWRATE_PIN9_Pos (9)
208 #define DRV_SX1509_LONGSLEWRATE_PIN9_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN9_Pos)
209 #define DRV_SX1509_LONGSLEWRATE_PIN9_Disabled (0)
210 #define DRV_SX1509_LONGSLEWRATE_PIN9_Enabled (1)
213 /* Field PIN8: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
214 #define DRV_SX1509_LONGSLEWRATE_PIN8_Pos (8)
215 #define DRV_SX1509_LONGSLEWRATE_PIN8_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN8_Pos)
216 #define DRV_SX1509_LONGSLEWRATE_PIN8_Disabled (0)
217 #define DRV_SX1509_LONGSLEWRATE_PIN8_Enabled (1)
220 /* Field PIN7: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
221 #define DRV_SX1509_LONGSLEWRATE_PIN7_Pos (7)
222 #define DRV_SX1509_LONGSLEWRATE_PIN7_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN7_Pos)
223 #define DRV_SX1509_LONGSLEWRATE_PIN7_Disabled (0)
224 #define DRV_SX1509_LONGSLEWRATE_PIN7_Enabled (1)
227 /* Field PIN6: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
228 #define DRV_SX1509_LONGSLEWRATE_PIN6_Pos (6)
229 #define DRV_SX1509_LONGSLEWRATE_PIN6_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN6_Pos)
230 #define DRV_SX1509_LONGSLEWRATE_PIN6_Disabled (0)
231 #define DRV_SX1509_LONGSLEWRATE_PIN6_Enabled (1)
234 /* Field PIN5: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
235 #define DRV_SX1509_LONGSLEWRATE_PIN5_Pos (5)
236 #define DRV_SX1509_LONGSLEWRATE_PIN5_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN5_Pos)
237 #define DRV_SX1509_LONGSLEWRATE_PIN5_Disabled (0)
238 #define DRV_SX1509_LONGSLEWRATE_PIN5_Enabled (1)
241 /* Field PIN4: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
242 #define DRV_SX1509_LONGSLEWRATE_PIN4_Pos (4)
243 #define DRV_SX1509_LONGSLEWRATE_PIN4_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN4_Pos)
244 #define DRV_SX1509_LONGSLEWRATE_PIN4_Disabled (0)
245 #define DRV_SX1509_LONGSLEWRATE_PIN4_Enabled (1)
248 /* Field PIN3: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
249 #define DRV_SX1509_LONGSLEWRATE_PIN3_Pos (3)
250 #define DRV_SX1509_LONGSLEWRATE_PIN3_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN3_Pos)
251 #define DRV_SX1509_LONGSLEWRATE_PIN3_Disabled (0)
252 #define DRV_SX1509_LONGSLEWRATE_PIN3_Enabled (1)
255 /* Field PIN2: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
256 #define DRV_SX1509_LONGSLEWRATE_PIN2_Pos (2)
257 #define DRV_SX1509_LONGSLEWRATE_PIN2_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN2_Pos)
258 #define DRV_SX1509_LONGSLEWRATE_PIN2_Disabled (0)
259 #define DRV_SX1509_LONGSLEWRATE_PIN2_Enabled (1)
262 /* Field PIN1: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
263 #define DRV_SX1509_LONGSLEWRATE_PIN1_Pos (1)
264 #define DRV_SX1509_LONGSLEWRATE_PIN1_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN1_Pos)
265 #define DRV_SX1509_LONGSLEWRATE_PIN1_Disabled (0)
266 #define DRV_SX1509_LONGSLEWRATE_PIN1_Enabled (1)
269 /* Field PIN0: Enables/Disables increased slew rate of the output buffer of each [output-configured] IO. */
270 #define DRV_SX1509_LONGSLEWRATE_PIN0_Pos (0)
271 #define DRV_SX1509_LONGSLEWRATE_PIN0_Msk (0x1 << DRV_SX1509_LONGSLEWRATE_PIN0_Pos)
272 #define DRV_SX1509_LONGSLEWRATE_PIN0_Disabled (0)
273 #define DRV_SX1509_LONGSLEWRATE_PIN0_Enabled (1)
276 /* Register: LOWDRIVE. */
277 /* Description: Output buffer low drive register. */
278
279
280 /* Field PIN15: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
281 #define DRV_SX1509_LOWDRIVE_PIN15_Pos (15)
282 #define DRV_SX1509_LOWDRIVE_PIN15_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN15_Pos)
283 #define DRV_SX1509_LOWDRIVE_PIN15_Disabled (0)
284 #define DRV_SX1509_LOWDRIVE_PIN15_Enabled (1)
287 /* Field PIN14: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
288 #define DRV_SX1509_LOWDRIVE_PIN14_Pos (14)
289 #define DRV_SX1509_LOWDRIVE_PIN14_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN14_Pos)
290 #define DRV_SX1509_LOWDRIVE_PIN14_Disabled (0)
291 #define DRV_SX1509_LOWDRIVE_PIN14_Enabled (1)
294 /* Field PIN13: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
295 #define DRV_SX1509_LOWDRIVE_PIN13_Pos (13)
296 #define DRV_SX1509_LOWDRIVE_PIN13_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN13_Pos)
297 #define DRV_SX1509_LOWDRIVE_PIN13_Disabled (0)
298 #define DRV_SX1509_LOWDRIVE_PIN13_Enabled (1)
301 /* Field PIN12: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
302 #define DRV_SX1509_LOWDRIVE_PIN12_Pos (12)
303 #define DRV_SX1509_LOWDRIVE_PIN12_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN12_Pos)
304 #define DRV_SX1509_LOWDRIVE_PIN12_Disabled (0)
305 #define DRV_SX1509_LOWDRIVE_PIN12_Enabled (1)
308 /* Field PIN11: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
309 #define DRV_SX1509_LOWDRIVE_PIN11_Pos (11)
310 #define DRV_SX1509_LOWDRIVE_PIN11_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN11_Pos)
311 #define DRV_SX1509_LOWDRIVE_PIN11_Disabled (0)
312 #define DRV_SX1509_LOWDRIVE_PIN11_Enabled (1)
315 /* Field PIN10: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
316 #define DRV_SX1509_LOWDRIVE_PIN10_Pos (10)
317 #define DRV_SX1509_LOWDRIVE_PIN10_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN10_Pos)
318 #define DRV_SX1509_LOWDRIVE_PIN10_Disabled (0)
319 #define DRV_SX1509_LOWDRIVE_PIN10_Enabled (1)
322 /* Field PIN9: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
323 #define DRV_SX1509_LOWDRIVE_PIN9_Pos (9)
324 #define DRV_SX1509_LOWDRIVE_PIN9_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN9_Pos)
325 #define DRV_SX1509_LOWDRIVE_PIN9_Disabled (0)
326 #define DRV_SX1509_LOWDRIVE_PIN9_Enabled (1)
329 /* Field PIN8: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
330 #define DRV_SX1509_LOWDRIVE_PIN8_Pos (8)
331 #define DRV_SX1509_LOWDRIVE_PIN8_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN8_Pos)
332 #define DRV_SX1509_LOWDRIVE_PIN8_Disabled (0)
333 #define DRV_SX1509_LOWDRIVE_PIN8_Enabled (1)
336 /* Field PIN7: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
337 #define DRV_SX1509_LOWDRIVE_PIN7_Pos (7)
338 #define DRV_SX1509_LOWDRIVE_PIN7_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN7_Pos)
339 #define DRV_SX1509_LOWDRIVE_PIN7_Disabled (0)
340 #define DRV_SX1509_LOWDRIVE_PIN7_Enabled (1)
343 /* Field PIN6: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
344 #define DRV_SX1509_LOWDRIVE_PIN6_Pos (6)
345 #define DRV_SX1509_LOWDRIVE_PIN6_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN6_Pos)
346 #define DRV_SX1509_LOWDRIVE_PIN6_Disabled (0)
347 #define DRV_SX1509_LOWDRIVE_PIN6_Enabled (1)
350 /* Field PIN5: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
351 #define DRV_SX1509_LOWDRIVE_PIN5_Pos (5)
352 #define DRV_SX1509_LOWDRIVE_PIN5_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN5_Pos)
353 #define DRV_SX1509_LOWDRIVE_PIN5_Disabled (0)
354 #define DRV_SX1509_LOWDRIVE_PIN5_Enabled (1)
357 /* Field PIN4: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
358 #define DRV_SX1509_LOWDRIVE_PIN4_Pos (4)
359 #define DRV_SX1509_LOWDRIVE_PIN4_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN4_Pos)
360 #define DRV_SX1509_LOWDRIVE_PIN4_Disabled (0)
361 #define DRV_SX1509_LOWDRIVE_PIN4_Enabled (1)
364 /* Field PIN3: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
365 #define DRV_SX1509_LOWDRIVE_PIN3_Pos (3)
366 #define DRV_SX1509_LOWDRIVE_PIN3_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN3_Pos)
367 #define DRV_SX1509_LOWDRIVE_PIN3_Disabled (0)
368 #define DRV_SX1509_LOWDRIVE_PIN3_Enabled (1)
371 /* Field PIN2: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
372 #define DRV_SX1509_LOWDRIVE_PIN2_Pos (2)
373 #define DRV_SX1509_LOWDRIVE_PIN2_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN2_Pos)
374 #define DRV_SX1509_LOWDRIVE_PIN2_Disabled (0)
375 #define DRV_SX1509_LOWDRIVE_PIN2_Enabled (1)
378 /* Field PIN1: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
379 #define DRV_SX1509_LOWDRIVE_PIN1_Pos (1)
380 #define DRV_SX1509_LOWDRIVE_PIN1_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN1_Pos)
381 #define DRV_SX1509_LOWDRIVE_PIN1_Disabled (0)
382 #define DRV_SX1509_LOWDRIVE_PIN1_Enabled (1)
385 /* Field PIN0: Enables/Disables reduced drive of the output buffer of each [output-configured] IO. */
386 #define DRV_SX1509_LOWDRIVE_PIN0_Pos (0)
387 #define DRV_SX1509_LOWDRIVE_PIN0_Msk (0x1 << DRV_SX1509_LOWDRIVE_PIN0_Pos)
388 #define DRV_SX1509_LOWDRIVE_PIN0_Disabled (0)
389 #define DRV_SX1509_LOWDRIVE_PIN0_Enabled (1)
392 /* Register: PULLUP. */
393 /* Description: Pull-up register. */
394
395
396 /* Field PIN15: Enables/Disables the pull-up for each IO. */
397 #define DRV_SX1509_PULLUP_PIN15_Pos (15)
398 #define DRV_SX1509_PULLUP_PIN15_Msk (0x1 << DRV_SX1509_PULLUP_PIN15_Pos)
399 #define DRV_SX1509_PULLUP_PIN15_Disabled (0)
400 #define DRV_SX1509_PULLUP_PIN15_Enabled (1)
403 /* Field PIN14: Enables/Disables the pull-up for each IO. */
404 #define DRV_SX1509_PULLUP_PIN14_Pos (14)
405 #define DRV_SX1509_PULLUP_PIN14_Msk (0x1 << DRV_SX1509_PULLUP_PIN14_Pos)
406 #define DRV_SX1509_PULLUP_PIN14_Disabled (0)
407 #define DRV_SX1509_PULLUP_PIN14_Enabled (1)
410 /* Field PIN13: Enables/Disables the pull-up for each IO. */
411 #define DRV_SX1509_PULLUP_PIN13_Pos (13)
412 #define DRV_SX1509_PULLUP_PIN13_Msk (0x1 << DRV_SX1509_PULLUP_PIN13_Pos)
413 #define DRV_SX1509_PULLUP_PIN13_Disabled (0)
414 #define DRV_SX1509_PULLUP_PIN13_Enabled (1)
417 /* Field PIN12: Enables/Disables the pull-up for each IO. */
418 #define DRV_SX1509_PULLUP_PIN12_Pos (12)
419 #define DRV_SX1509_PULLUP_PIN12_Msk (0x1 << DRV_SX1509_PULLUP_PIN12_Pos)
420 #define DRV_SX1509_PULLUP_PIN12_Disabled (0)
421 #define DRV_SX1509_PULLUP_PIN12_Enabled (1)
424 /* Field PIN11: Enables/Disables the pull-up for each IO. */
425 #define DRV_SX1509_PULLUP_PIN11_Pos (11)
426 #define DRV_SX1509_PULLUP_PIN11_Msk (0x1 << DRV_SX1509_PULLUP_PIN11_Pos)
427 #define DRV_SX1509_PULLUP_PIN11_Disabled (0)
428 #define DRV_SX1509_PULLUP_PIN11_Enabled (1)
431 /* Field PIN10: Enables/Disables the pull-up for each IO. */
432 #define DRV_SX1509_PULLUP_PIN10_Pos (10)
433 #define DRV_SX1509_PULLUP_PIN10_Msk (0x1 << DRV_SX1509_PULLUP_PIN10_Pos)
434 #define DRV_SX1509_PULLUP_PIN10_Disabled (0)
435 #define DRV_SX1509_PULLUP_PIN10_Enabled (1)
438 /* Field PIN9: Enables/Disables the pull-up for each IO. */
439 #define DRV_SX1509_PULLUP_PIN9_Pos (9)
440 #define DRV_SX1509_PULLUP_PIN9_Msk (0x1 << DRV_SX1509_PULLUP_PIN9_Pos)
441 #define DRV_SX1509_PULLUP_PIN9_Disabled (0)
442 #define DRV_SX1509_PULLUP_PIN9_Enabled (1)
445 /* Field PIN8: Enables/Disables the pull-up for each IO. */
446 #define DRV_SX1509_PULLUP_PIN8_Pos (8)
447 #define DRV_SX1509_PULLUP_PIN8_Msk (0x1 << DRV_SX1509_PULLUP_PIN8_Pos)
448 #define DRV_SX1509_PULLUP_PIN8_Disabled (0)
449 #define DRV_SX1509_PULLUP_PIN8_Enabled (1)
452 /* Field PIN7: Enables/Disables the pull-up for each IO. */
453 #define DRV_SX1509_PULLUP_PIN7_Pos (7)
454 #define DRV_SX1509_PULLUP_PIN7_Msk (0x1 << DRV_SX1509_PULLUP_PIN7_Pos)
455 #define DRV_SX1509_PULLUP_PIN7_Disabled (0)
456 #define DRV_SX1509_PULLUP_PIN7_Enabled (1)
459 /* Field PIN6: Enables/Disables the pull-up for each IO. */
460 #define DRV_SX1509_PULLUP_PIN6_Pos (6)
461 #define DRV_SX1509_PULLUP_PIN6_Msk (0x1 << DRV_SX1509_PULLUP_PIN6_Pos)
462 #define DRV_SX1509_PULLUP_PIN6_Disabled (0)
463 #define DRV_SX1509_PULLUP_PIN6_Enabled (1)
466 /* Field PIN5: Enables/Disables the pull-up for each IO. */
467 #define DRV_SX1509_PULLUP_PIN5_Pos (5)
468 #define DRV_SX1509_PULLUP_PIN5_Msk (0x1 << DRV_SX1509_PULLUP_PIN5_Pos)
469 #define DRV_SX1509_PULLUP_PIN5_Disabled (0)
470 #define DRV_SX1509_PULLUP_PIN5_Enabled (1)
473 /* Field PIN4: Enables/Disables the pull-up for each IO. */
474 #define DRV_SX1509_PULLUP_PIN4_Pos (4)
475 #define DRV_SX1509_PULLUP_PIN4_Msk (0x1 << DRV_SX1509_PULLUP_PIN4_Pos)
476 #define DRV_SX1509_PULLUP_PIN4_Disabled (0)
477 #define DRV_SX1509_PULLUP_PIN4_Enabled (1)
480 /* Field PIN3: Enables/Disables the pull-up for each IO. */
481 #define DRV_SX1509_PULLUP_PIN3_Pos (3)
482 #define DRV_SX1509_PULLUP_PIN3_Msk (0x1 << DRV_SX1509_PULLUP_PIN3_Pos)
483 #define DRV_SX1509_PULLUP_PIN3_Disabled (0)
484 #define DRV_SX1509_PULLUP_PIN3_Enabled (1)
487 /* Field PIN2: Enables/Disables the pull-up for each IO. */
488 #define DRV_SX1509_PULLUP_PIN2_Pos (2)
489 #define DRV_SX1509_PULLUP_PIN2_Msk (0x1 << DRV_SX1509_PULLUP_PIN2_Pos)
490 #define DRV_SX1509_PULLUP_PIN2_Disabled (0)
491 #define DRV_SX1509_PULLUP_PIN2_Enabled (1)
494 /* Field PIN1: Enables/Disables the pull-up for each IO. */
495 #define DRV_SX1509_PULLUP_PIN1_Pos (1)
496 #define DRV_SX1509_PULLUP_PIN1_Msk (0x1 << DRV_SX1509_PULLUP_PIN1_Pos)
497 #define DRV_SX1509_PULLUP_PIN1_Disabled (0)
498 #define DRV_SX1509_PULLUP_PIN1_Enabled (1)
501 /* Field PIN0: Enables/Disables the pull-up for each IO. */
502 #define DRV_SX1509_PULLUP_PIN0_Pos (0)
503 #define DRV_SX1509_PULLUP_PIN0_Msk (0x1 << DRV_SX1509_PULLUP_PIN0_Pos)
504 #define DRV_SX1509_PULLUP_PIN0_Disabled (0)
505 #define DRV_SX1509_PULLUP_PIN0_Enabled (1)
508 /* Register: PULLDOWN. */
509 /* Description: Pull-down register. */
510
511
512 /* Field PIN15: Enables/Disables pull-down for each IO. */
513 #define DRV_SX1509_PULLDOWN_PIN15_Pos (15)
514 #define DRV_SX1509_PULLDOWN_PIN15_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN15_Pos)
515 #define DRV_SX1509_PULLDOWN_PIN15_Disabled (0)
516 #define DRV_SX1509_PULLDOWN_PIN15_Enabled (1)
519 /* Field PIN14: Enables/Disables pull-down for each IO. */
520 #define DRV_SX1509_PULLDOWN_PIN14_Pos (14)
521 #define DRV_SX1509_PULLDOWN_PIN14_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN14_Pos)
522 #define DRV_SX1509_PULLDOWN_PIN14_Disabled (0)
523 #define DRV_SX1509_PULLDOWN_PIN14_Enabled (1)
526 /* Field PIN13: Enables/Disables pull-down for each IO. */
527 #define DRV_SX1509_PULLDOWN_PIN13_Pos (13)
528 #define DRV_SX1509_PULLDOWN_PIN13_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN13_Pos)
529 #define DRV_SX1509_PULLDOWN_PIN13_Disabled (0)
530 #define DRV_SX1509_PULLDOWN_PIN13_Enabled (1)
533 /* Field PIN12: Enables/Disables pull-down for each IO. */
534 #define DRV_SX1509_PULLDOWN_PIN12_Pos (12)
535 #define DRV_SX1509_PULLDOWN_PIN12_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN12_Pos)
536 #define DRV_SX1509_PULLDOWN_PIN12_Disabled (0)
537 #define DRV_SX1509_PULLDOWN_PIN12_Enabled (1)
540 /* Field PIN11: Enables/Disables pull-down for each IO. */
541 #define DRV_SX1509_PULLDOWN_PIN11_Pos (11)
542 #define DRV_SX1509_PULLDOWN_PIN11_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN11_Pos)
543 #define DRV_SX1509_PULLDOWN_PIN11_Disabled (0)
544 #define DRV_SX1509_PULLDOWN_PIN11_Enabled (1)
547 /* Field PIN10: Enables/Disables pull-down for each IO. */
548 #define DRV_SX1509_PULLDOWN_PIN10_Pos (10)
549 #define DRV_SX1509_PULLDOWN_PIN10_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN10_Pos)
550 #define DRV_SX1509_PULLDOWN_PIN10_Disabled (0)
551 #define DRV_SX1509_PULLDOWN_PIN10_Enabled (1)
554 /* Field PIN9: Enables/Disables pull-down for each IO. */
555 #define DRV_SX1509_PULLDOWN_PIN9_Pos (9)
556 #define DRV_SX1509_PULLDOWN_PIN9_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN9_Pos)
557 #define DRV_SX1509_PULLDOWN_PIN9_Disabled (0)
558 #define DRV_SX1509_PULLDOWN_PIN9_Enabled (1)
561 /* Field PIN8: Enables/Disables pull-down for each IO. */
562 #define DRV_SX1509_PULLDOWN_PIN8_Pos (8)
563 #define DRV_SX1509_PULLDOWN_PIN8_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN8_Pos)
564 #define DRV_SX1509_PULLDOWN_PIN8_Disabled (0)
565 #define DRV_SX1509_PULLDOWN_PIN8_Enabled (1)
568 /* Field PIN7: Enables/Disables pull-down for each IO. */
569 #define DRV_SX1509_PULLDOWN_PIN7_Pos (7)
570 #define DRV_SX1509_PULLDOWN_PIN7_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN7_Pos)
571 #define DRV_SX1509_PULLDOWN_PIN7_Disabled (0)
572 #define DRV_SX1509_PULLDOWN_PIN7_Enabled (1)
575 /* Field PIN6: Enables/Disables pull-down for each IO. */
576 #define DRV_SX1509_PULLDOWN_PIN6_Pos (6)
577 #define DRV_SX1509_PULLDOWN_PIN6_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN6_Pos)
578 #define DRV_SX1509_PULLDOWN_PIN6_Disabled (0)
579 #define DRV_SX1509_PULLDOWN_PIN6_Enabled (1)
582 /* Field PIN5: Enables/Disables pull-down for each IO. */
583 #define DRV_SX1509_PULLDOWN_PIN5_Pos (5)
584 #define DRV_SX1509_PULLDOWN_PIN5_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN5_Pos)
585 #define DRV_SX1509_PULLDOWN_PIN5_Disabled (0)
586 #define DRV_SX1509_PULLDOWN_PIN5_Enabled (1)
589 /* Field PIN4: Enables/Disables pull-down for each IO. */
590 #define DRV_SX1509_PULLDOWN_PIN4_Pos (4)
591 #define DRV_SX1509_PULLDOWN_PIN4_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN4_Pos)
592 #define DRV_SX1509_PULLDOWN_PIN4_Disabled (0)
593 #define DRV_SX1509_PULLDOWN_PIN4_Enabled (1)
596 /* Field PIN3: Enables/Disables pull-down for each IO. */
597 #define DRV_SX1509_PULLDOWN_PIN3_Pos (3)
598 #define DRV_SX1509_PULLDOWN_PIN3_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN3_Pos)
599 #define DRV_SX1509_PULLDOWN_PIN3_Disabled (0)
600 #define DRV_SX1509_PULLDOWN_PIN3_Enabled (1)
603 /* Field PIN2: Enables/Disables pull-down for each IO. */
604 #define DRV_SX1509_PULLDOWN_PIN2_Pos (2)
605 #define DRV_SX1509_PULLDOWN_PIN2_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN2_Pos)
606 #define DRV_SX1509_PULLDOWN_PIN2_Disabled (0)
607 #define DRV_SX1509_PULLDOWN_PIN2_Enabled (1)
610 /* Field PIN1: Enables/Disables pull-down for each IO. */
611 #define DRV_SX1509_PULLDOWN_PIN1_Pos (1)
612 #define DRV_SX1509_PULLDOWN_PIN1_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN1_Pos)
613 #define DRV_SX1509_PULLDOWN_PIN1_Disabled (0)
614 #define DRV_SX1509_PULLDOWN_PIN1_Enabled (1)
617 /* Field PIN0: Enables/Disables pull-down for each IO. */
618 #define DRV_SX1509_PULLDOWN_PIN0_Pos (0)
619 #define DRV_SX1509_PULLDOWN_PIN0_Msk (0x1 << DRV_SX1509_PULLDOWN_PIN0_Pos)
620 #define DRV_SX1509_PULLDOWN_PIN0_Disabled (0)
621 #define DRV_SX1509_PULLDOWN_PIN0_Enabled (1)
624 /* Register: OPENDRAIN. */
625 /* Description: Enables/Disables open drain operation for each [output-configured] IO. */
626
627
628 /* Field PIN15: Enables/Disables open drain operation for each [output-configured] IO. */
629 #define DRV_SX1509_OPENDRAIN_PIN15_Pos (15)
630 #define DRV_SX1509_OPENDRAIN_PIN15_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN15_Pos)
631 #define DRV_SX1509_OPENDRAIN_PIN15_PushPull (0)
632 #define DRV_SX1509_OPENDRAIN_PIN15_OpenDrain (1)
635 /* Field PIN14: Enables/Disables open drain operation for each [output-configured] IO. */
636 #define DRV_SX1509_OPENDRAIN_PIN14_Pos (14)
637 #define DRV_SX1509_OPENDRAIN_PIN14_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN14_Pos)
638 #define DRV_SX1509_OPENDRAIN_PIN14_PushPull (0)
639 #define DRV_SX1509_OPENDRAIN_PIN14_OpenDrain (1)
642 /* Field PIN13: Enables/Disables open drain operation for each [output-configured] IO. */
643 #define DRV_SX1509_OPENDRAIN_PIN13_Pos (13)
644 #define DRV_SX1509_OPENDRAIN_PIN13_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN13_Pos)
645 #define DRV_SX1509_OPENDRAIN_PIN13_PushPull (0)
646 #define DRV_SX1509_OPENDRAIN_PIN13_OpenDrain (1)
649 /* Field PIN12: Enables/Disables open drain operation for each [output-configured] IO. */
650 #define DRV_SX1509_OPENDRAIN_PIN12_Pos (12)
651 #define DRV_SX1509_OPENDRAIN_PIN12_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN12_Pos)
652 #define DRV_SX1509_OPENDRAIN_PIN12_PushPull (0)
653 #define DRV_SX1509_OPENDRAIN_PIN12_OpenDrain (1)
656 /* Field PIN11: Enables/Disables open drain operation for each [output-configured] IO. */
657 #define DRV_SX1509_OPENDRAIN_PIN11_Pos (11)
658 #define DRV_SX1509_OPENDRAIN_PIN11_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN11_Pos)
659 #define DRV_SX1509_OPENDRAIN_PIN11_PushPull (0)
660 #define DRV_SX1509_OPENDRAIN_PIN11_OpenDrain (1)
663 /* Field PIN10: Enables/Disables open drain operation for each [output-configured] IO. */
664 #define DRV_SX1509_OPENDRAIN_PIN10_Pos (10)
665 #define DRV_SX1509_OPENDRAIN_PIN10_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN10_Pos)
666 #define DRV_SX1509_OPENDRAIN_PIN10_PushPull (0)
667 #define DRV_SX1509_OPENDRAIN_PIN10_OpenDrain (1)
670 /* Field PIN9: Enables/Disables open drain operation for each [output-configured] IO. */
671 #define DRV_SX1509_OPENDRAIN_PIN9_Pos (9)
672 #define DRV_SX1509_OPENDRAIN_PIN9_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN9_Pos)
673 #define DRV_SX1509_OPENDRAIN_PIN9_PushPull (0)
674 #define DRV_SX1509_OPENDRAIN_PIN9_OpenDrain (1)
677 /* Field PIN8: Enables/Disables open drain operation for each [output-configured] IO. */
678 #define DRV_SX1509_OPENDRAIN_PIN8_Pos (8)
679 #define DRV_SX1509_OPENDRAIN_PIN8_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN8_Pos)
680 #define DRV_SX1509_OPENDRAIN_PIN8_PushPull (0)
681 #define DRV_SX1509_OPENDRAIN_PIN8_OpenDrain (1)
684 /* Field PIN7: Enables/Disables open drain operation for each [output-configured] IO. */
685 #define DRV_SX1509_OPENDRAIN_PIN7_Pos (7)
686 #define DRV_SX1509_OPENDRAIN_PIN7_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN7_Pos)
687 #define DRV_SX1509_OPENDRAIN_PIN7_PushPull (0)
688 #define DRV_SX1509_OPENDRAIN_PIN7_OpenDrain (1)
691 /* Field PIN6: Enables/Disables open drain operation for each [output-configured] IO. */
692 #define DRV_SX1509_OPENDRAIN_PIN6_Pos (6)
693 #define DRV_SX1509_OPENDRAIN_PIN6_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN6_Pos)
694 #define DRV_SX1509_OPENDRAIN_PIN6_PushPull (0)
695 #define DRV_SX1509_OPENDRAIN_PIN6_OpenDrain (1)
698 /* Field PIN5: Enables/Disables open drain operation for each [output-configured] IO. */
699 #define DRV_SX1509_OPENDRAIN_PIN5_Pos (5)
700 #define DRV_SX1509_OPENDRAIN_PIN5_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN5_Pos)
701 #define DRV_SX1509_OPENDRAIN_PIN5_PushPull (0)
702 #define DRV_SX1509_OPENDRAIN_PIN5_OpenDrain (1)
705 /* Field PIN4: Enables/Disables open drain operation for each [output-configured] IO. */
706 #define DRV_SX1509_OPENDRAIN_PIN4_Pos (4)
707 #define DRV_SX1509_OPENDRAIN_PIN4_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN4_Pos)
708 #define DRV_SX1509_OPENDRAIN_PIN4_PushPull (0)
709 #define DRV_SX1509_OPENDRAIN_PIN4_OpenDrain (1)
712 /* Field PIN3: Enables/Disables open drain operation for each [output-configured] IO. */
713 #define DRV_SX1509_OPENDRAIN_PIN3_Pos (3)
714 #define DRV_SX1509_OPENDRAIN_PIN3_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN3_Pos)
715 #define DRV_SX1509_OPENDRAIN_PIN3_PushPull (0)
716 #define DRV_SX1509_OPENDRAIN_PIN3_OpenDrain (1)
719 /* Field PIN2: Enables/Disables open drain operation for each [output-configured] IO. */
720 #define DRV_SX1509_OPENDRAIN_PIN2_Pos (2)
721 #define DRV_SX1509_OPENDRAIN_PIN2_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN2_Pos)
722 #define DRV_SX1509_OPENDRAIN_PIN2_PushPull (0)
723 #define DRV_SX1509_OPENDRAIN_PIN2_OpenDrain (1)
726 /* Field PIN1: Enables/Disables open drain operation for each [output-configured] IO. */
727 #define DRV_SX1509_OPENDRAIN_PIN1_Pos (1)
728 #define DRV_SX1509_OPENDRAIN_PIN1_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN1_Pos)
729 #define DRV_SX1509_OPENDRAIN_PIN1_PushPull (0)
730 #define DRV_SX1509_OPENDRAIN_PIN1_OpenDrain (1)
733 /* Field PIN0: Enables/Disables open drain operation for each [output-configured] IO. */
734 #define DRV_SX1509_OPENDRAIN_PIN0_Pos (0)
735 #define DRV_SX1509_OPENDRAIN_PIN0_Msk (0x1 << DRV_SX1509_OPENDRAIN_PIN0_Pos)
736 #define DRV_SX1509_OPENDRAIN_PIN0_PushPull (0)
737 #define DRV_SX1509_OPENDRAIN_PIN0_OpenDrain (1)
740 /* Register: POLARITY. */
741 /* Description: Enables/Disables polarity inversion for each IO. */
742
743
744 /* Field PIN15: Enables/Disables polarity inversion for each IO. */
745 #define DRV_SX1509_POLARITY_PIN15_Pos (15)
746 #define DRV_SX1509_POLARITY_PIN15_Msk (0x1 << DRV_SX1509_POLARITY_PIN15_Pos)
747 #define DRV_SX1509_POLARITY_PIN15_Normal (0)
748 #define DRV_SX1509_POLARITY_PIN15_Inverted (1)
751 /* Field PIN14: Enables/Disables polarity inversion for each IO. */
752 #define DRV_SX1509_POLARITY_PIN14_Pos (14)
753 #define DRV_SX1509_POLARITY_PIN14_Msk (0x1 << DRV_SX1509_POLARITY_PIN14_Pos)
754 #define DRV_SX1509_POLARITY_PIN14_Normal (0)
755 #define DRV_SX1509_POLARITY_PIN14_Inverted (1)
758 /* Field PIN13: Enables/Disables polarity inversion for each IO. */
759 #define DRV_SX1509_POLARITY_PIN13_Pos (13)
760 #define DRV_SX1509_POLARITY_PIN13_Msk (0x1 << DRV_SX1509_POLARITY_PIN13_Pos)
761 #define DRV_SX1509_POLARITY_PIN13_Normal (0)
762 #define DRV_SX1509_POLARITY_PIN13_Inverted (1)
765 /* Field PIN12: Enables/Disables polarity inversion for each IO. */
766 #define DRV_SX1509_POLARITY_PIN12_Pos (12)
767 #define DRV_SX1509_POLARITY_PIN12_Msk (0x1 << DRV_SX1509_POLARITY_PIN12_Pos)
768 #define DRV_SX1509_POLARITY_PIN12_Normal (0)
769 #define DRV_SX1509_POLARITY_PIN12_Inverted (1)
772 /* Field PIN11: Enables/Disables polarity inversion for each IO. */
773 #define DRV_SX1509_POLARITY_PIN11_Pos (11)
774 #define DRV_SX1509_POLARITY_PIN11_Msk (0x1 << DRV_SX1509_POLARITY_PIN11_Pos)
775 #define DRV_SX1509_POLARITY_PIN11_Normal (0)
776 #define DRV_SX1509_POLARITY_PIN11_Inverted (1)
779 /* Field PIN10: Enables/Disables polarity inversion for each IO. */
780 #define DRV_SX1509_POLARITY_PIN10_Pos (10)
781 #define DRV_SX1509_POLARITY_PIN10_Msk (0x1 << DRV_SX1509_POLARITY_PIN10_Pos)
782 #define DRV_SX1509_POLARITY_PIN10_Normal (0)
783 #define DRV_SX1509_POLARITY_PIN10_Inverted (1)
786 /* Field PIN9: Enables/Disables polarity inversion for each IO. */
787 #define DRV_SX1509_POLARITY_PIN9_Pos (9)
788 #define DRV_SX1509_POLARITY_PIN9_Msk (0x1 << DRV_SX1509_POLARITY_PIN9_Pos)
789 #define DRV_SX1509_POLARITY_PIN9_Normal (0)
790 #define DRV_SX1509_POLARITY_PIN9_Inverted (1)
793 /* Field PIN8: Enables/Disables polarity inversion for each IO. */
794 #define DRV_SX1509_POLARITY_PIN8_Pos (8)
795 #define DRV_SX1509_POLARITY_PIN8_Msk (0x1 << DRV_SX1509_POLARITY_PIN8_Pos)
796 #define DRV_SX1509_POLARITY_PIN8_Normal (0)
797 #define DRV_SX1509_POLARITY_PIN8_Inverted (1)
800 /* Field PIN7: Enables/Disables polarity inversion for each IO. */
801 #define DRV_SX1509_POLARITY_PIN7_Pos (7)
802 #define DRV_SX1509_POLARITY_PIN7_Msk (0x1 << DRV_SX1509_POLARITY_PIN7_Pos)
803 #define DRV_SX1509_POLARITY_PIN7_Normal (0)
804 #define DRV_SX1509_POLARITY_PIN7_Inverted (1)
807 /* Field PIN6: Enables/Disables polarity inversion for each IO. */
808 #define DRV_SX1509_POLARITY_PIN6_Pos (6)
809 #define DRV_SX1509_POLARITY_PIN6_Msk (0x1 << DRV_SX1509_POLARITY_PIN6_Pos)
810 #define DRV_SX1509_POLARITY_PIN6_Normal (0)
811 #define DRV_SX1509_POLARITY_PIN6_Inverted (1)
814 /* Field PIN5: Enables/Disables polarity inversion for each IO. */
815 #define DRV_SX1509_POLARITY_PIN5_Pos (5)
816 #define DRV_SX1509_POLARITY_PIN5_Msk (0x1 << DRV_SX1509_POLARITY_PIN5_Pos)
817 #define DRV_SX1509_POLARITY_PIN5_Normal (0)
818 #define DRV_SX1509_POLARITY_PIN5_Inverted (1)
821 /* Field PIN4: Enables/Disables polarity inversion for each IO. */
822 #define DRV_SX1509_POLARITY_PIN4_Pos (4)
823 #define DRV_SX1509_POLARITY_PIN4_Msk (0x1 << DRV_SX1509_POLARITY_PIN4_Pos)
824 #define DRV_SX1509_POLARITY_PIN4_Normal (0)
825 #define DRV_SX1509_POLARITY_PIN4_Inverted (1)
828 /* Field PIN3: Enables/Disables polarity inversion for each IO. */
829 #define DRV_SX1509_POLARITY_PIN3_Pos (3)
830 #define DRV_SX1509_POLARITY_PIN3_Msk (0x1 << DRV_SX1509_POLARITY_PIN3_Pos)
831 #define DRV_SX1509_POLARITY_PIN3_Normal (0)
832 #define DRV_SX1509_POLARITY_PIN3_Inverted (1)
835 /* Field PIN2: Enables/Disables polarity inversion for each IO. */
836 #define DRV_SX1509_POLARITY_PIN2_Pos (2)
837 #define DRV_SX1509_POLARITY_PIN2_Msk (0x1 << DRV_SX1509_POLARITY_PIN2_Pos)
838 #define DRV_SX1509_POLARITY_PIN2_Normal (0)
839 #define DRV_SX1509_POLARITY_PIN2_Inverted (1)
842 /* Field PIN1: Enables/Disables polarity inversion for each IO. */
843 #define DRV_SX1509_POLARITY_PIN1_Pos (1)
844 #define DRV_SX1509_POLARITY_PIN1_Msk (0x1 << DRV_SX1509_POLARITY_PIN1_Pos)
845 #define DRV_SX1509_POLARITY_PIN1_Normal (0)
846 #define DRV_SX1509_POLARITY_PIN1_Inverted (1)
849 /* Field PIN0: Enables/Disables polarity inversion for each IO. */
850 #define DRV_SX1509_POLARITY_PIN0_Pos (0)
851 #define DRV_SX1509_POLARITY_PIN0_Msk (0x1 << DRV_SX1509_POLARITY_PIN0_Pos)
852 #define DRV_SX1509_POLARITY_PIN0_Normal (0)
853 #define DRV_SX1509_POLARITY_PIN0_Inverted (1)
856 /* Register: DIR. */
857 /* Description: Configures direction for each IO. */
858
859
860 /* Field PIN15: Configures direction for each IO. */
861 #define DRV_SX1509_DIR_PIN15_Pos (15)
862 #define DRV_SX1509_DIR_PIN15_Msk (0x1 << DRV_SX1509_DIR_PIN15_Pos)
863 #define DRV_SX1509_DIR_PIN15_Output (0)
864 #define DRV_SX1509_DIR_PIN15_Input (1)
867 /* Field PIN14: Configures direction for each IO. */
868 #define DRV_SX1509_DIR_PIN14_Pos (14)
869 #define DRV_SX1509_DIR_PIN14_Msk (0x1 << DRV_SX1509_DIR_PIN14_Pos)
870 #define DRV_SX1509_DIR_PIN14_Output (0)
871 #define DRV_SX1509_DIR_PIN14_Input (1)
874 /* Field PIN13: Configures direction for each IO. */
875 #define DRV_SX1509_DIR_PIN13_Pos (13)
876 #define DRV_SX1509_DIR_PIN13_Msk (0x1 << DRV_SX1509_DIR_PIN13_Pos)
877 #define DRV_SX1509_DIR_PIN13_Output (0)
878 #define DRV_SX1509_DIR_PIN13_Input (1)
881 /* Field PIN12: Configures direction for each IO. */
882 #define DRV_SX1509_DIR_PIN12_Pos (12)
883 #define DRV_SX1509_DIR_PIN12_Msk (0x1 << DRV_SX1509_DIR_PIN12_Pos)
884 #define DRV_SX1509_DIR_PIN12_Output (0)
885 #define DRV_SX1509_DIR_PIN12_Input (1)
888 /* Field PIN11: Configures direction for each IO. */
889 #define DRV_SX1509_DIR_PIN11_Pos (11)
890 #define DRV_SX1509_DIR_PIN11_Msk (0x1 << DRV_SX1509_DIR_PIN11_Pos)
891 #define DRV_SX1509_DIR_PIN11_Output (0)
892 #define DRV_SX1509_DIR_PIN11_Input (1)
895 /* Field PIN10: Configures direction for each IO. */
896 #define DRV_SX1509_DIR_PIN10_Pos (10)
897 #define DRV_SX1509_DIR_PIN10_Msk (0x1 << DRV_SX1509_DIR_PIN10_Pos)
898 #define DRV_SX1509_DIR_PIN10_Output (0)
899 #define DRV_SX1509_DIR_PIN10_Input (1)
902 /* Field PIN9: Configures direction for each IO. */
903 #define DRV_SX1509_DIR_PIN9_Pos (9)
904 #define DRV_SX1509_DIR_PIN9_Msk (0x1 << DRV_SX1509_DIR_PIN9_Pos)
905 #define DRV_SX1509_DIR_PIN9_Output (0)
906 #define DRV_SX1509_DIR_PIN9_Input (1)
909 /* Field PIN8: Configures direction for each IO. */
910 #define DRV_SX1509_DIR_PIN8_Pos (8)
911 #define DRV_SX1509_DIR_PIN8_Msk (0x1 << DRV_SX1509_DIR_PIN8_Pos)
912 #define DRV_SX1509_DIR_PIN8_Output (0)
913 #define DRV_SX1509_DIR_PIN8_Input (1)
916 /* Field PIN7: Configures direction for each IO. */
917 #define DRV_SX1509_DIR_PIN7_Pos (7)
918 #define DRV_SX1509_DIR_PIN7_Msk (0x1 << DRV_SX1509_DIR_PIN7_Pos)
919 #define DRV_SX1509_DIR_PIN7_Output (0)
920 #define DRV_SX1509_DIR_PIN7_Input (1)
923 /* Field PIN6: Configures direction for each IO. */
924 #define DRV_SX1509_DIR_PIN6_Pos (6)
925 #define DRV_SX1509_DIR_PIN6_Msk (0x1 << DRV_SX1509_DIR_PIN6_Pos)
926 #define DRV_SX1509_DIR_PIN6_Output (0)
927 #define DRV_SX1509_DIR_PIN6_Input (1)
930 /* Field PIN5: Configures direction for each IO. */
931 #define DRV_SX1509_DIR_PIN5_Pos (5)
932 #define DRV_SX1509_DIR_PIN5_Msk (0x1 << DRV_SX1509_DIR_PIN5_Pos)
933 #define DRV_SX1509_DIR_PIN5_Output (0)
934 #define DRV_SX1509_DIR_PIN5_Input (1)
937 /* Field PIN4: Configures direction for each IO. */
938 #define DRV_SX1509_DIR_PIN4_Pos (4)
939 #define DRV_SX1509_DIR_PIN4_Msk (0x1 << DRV_SX1509_DIR_PIN4_Pos)
940 #define DRV_SX1509_DIR_PIN4_Output (0)
941 #define DRV_SX1509_DIR_PIN4_Input (1)
944 /* Field PIN3: Configures direction for each IO. */
945 #define DRV_SX1509_DIR_PIN3_Pos (3)
946 #define DRV_SX1509_DIR_PIN3_Msk (0x1 << DRV_SX1509_DIR_PIN3_Pos)
947 #define DRV_SX1509_DIR_PIN3_Output (0)
948 #define DRV_SX1509_DIR_PIN3_Input (1)
951 /* Field PIN2: Configures direction for each IO. */
952 #define DRV_SX1509_DIR_PIN2_Pos (2)
953 #define DRV_SX1509_DIR_PIN2_Msk (0x1 << DRV_SX1509_DIR_PIN2_Pos)
954 #define DRV_SX1509_DIR_PIN2_Output (0)
955 #define DRV_SX1509_DIR_PIN2_Input (1)
958 /* Field PIN1: Configures direction for each IO. */
959 #define DRV_SX1509_DIR_PIN1_Pos (1)
960 #define DRV_SX1509_DIR_PIN1_Msk (0x1 << DRV_SX1509_DIR_PIN1_Pos)
961 #define DRV_SX1509_DIR_PIN1_Output (0)
962 #define DRV_SX1509_DIR_PIN1_Input (1)
965 /* Field PIN0: Configures direction for each IO. */
966 #define DRV_SX1509_DIR_PIN0_Pos (0)
967 #define DRV_SX1509_DIR_PIN0_Msk (0x1 << DRV_SX1509_DIR_PIN0_Pos)
968 #define DRV_SX1509_DIR_PIN0_Output (0)
969 #define DRV_SX1509_DIR_PIN0_Input (1)
972 /* Register: DATA. */
973 /* Description: Data register - I/O. */
974
975
976 /* Field PIN15: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
977 #define DRV_SX1509_DATA_PIN15_Pos (15)
978 #define DRV_SX1509_DATA_PIN15_Msk (0x1 << DRV_SX1509_DATA_PIN15_Pos)
979 #define DRV_SX1509_DATA_PIN15_Low (0)
980 #define DRV_SX1509_DATA_PIN15_High (1)
983 /* Field PIN14: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
984 #define DRV_SX1509_DATA_PIN14_Pos (14)
985 #define DRV_SX1509_DATA_PIN14_Msk (0x1 << DRV_SX1509_DATA_PIN14_Pos)
986 #define DRV_SX1509_DATA_PIN14_Low (0)
987 #define DRV_SX1509_DATA_PIN14_High (1)
990 /* Field PIN13: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
991 #define DRV_SX1509_DATA_PIN13_Pos (13)
992 #define DRV_SX1509_DATA_PIN13_Msk (0x1 << DRV_SX1509_DATA_PIN13_Pos)
993 #define DRV_SX1509_DATA_PIN13_Low (0)
994 #define DRV_SX1509_DATA_PIN13_High (1)
997 /* Field PIN12: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
998 #define DRV_SX1509_DATA_PIN12_Pos (12)
999 #define DRV_SX1509_DATA_PIN12_Msk (0x1 << DRV_SX1509_DATA_PIN12_Pos)
1000 #define DRV_SX1509_DATA_PIN12_Low (0)
1001 #define DRV_SX1509_DATA_PIN12_High (1)
1004 /* Field PIN11: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1005 #define DRV_SX1509_DATA_PIN11_Pos (11)
1006 #define DRV_SX1509_DATA_PIN11_Msk (0x1 << DRV_SX1509_DATA_PIN11_Pos)
1007 #define DRV_SX1509_DATA_PIN11_Low (0)
1008 #define DRV_SX1509_DATA_PIN11_High (1)
1011 /* Field PIN10: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1012 #define DRV_SX1509_DATA_PIN10_Pos (10)
1013 #define DRV_SX1509_DATA_PIN10_Msk (0x1 << DRV_SX1509_DATA_PIN10_Pos)
1014 #define DRV_SX1509_DATA_PIN10_Low (0)
1015 #define DRV_SX1509_DATA_PIN10_High (1)
1018 /* Field PIN9: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1019 #define DRV_SX1509_DATA_PIN9_Pos (9)
1020 #define DRV_SX1509_DATA_PIN9_Msk (0x1 << DRV_SX1509_DATA_PIN9_Pos)
1021 #define DRV_SX1509_DATA_PIN9_Low (0)
1022 #define DRV_SX1509_DATA_PIN9_High (1)
1025 /* Field PIN8: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1026 #define DRV_SX1509_DATA_PIN8_Pos (8)
1027 #define DRV_SX1509_DATA_PIN8_Msk (0x1 << DRV_SX1509_DATA_PIN8_Pos)
1028 #define DRV_SX1509_DATA_PIN8_Low (0)
1029 #define DRV_SX1509_DATA_PIN8_High (1)
1032 /* Field PIN7: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1033 #define DRV_SX1509_DATA_PIN7_Pos (7)
1034 #define DRV_SX1509_DATA_PIN7_Msk (0x1 << DRV_SX1509_DATA_PIN7_Pos)
1035 #define DRV_SX1509_DATA_PIN7_Low (0)
1036 #define DRV_SX1509_DATA_PIN7_High (1)
1039 /* Field PIN6: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1040 #define DRV_SX1509_DATA_PIN6_Pos (6)
1041 #define DRV_SX1509_DATA_PIN6_Msk (0x1 << DRV_SX1509_DATA_PIN6_Pos)
1042 #define DRV_SX1509_DATA_PIN6_Low (0)
1043 #define DRV_SX1509_DATA_PIN6_High (1)
1046 /* Field PIN5: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1047 #define DRV_SX1509_DATA_PIN5_Pos (5)
1048 #define DRV_SX1509_DATA_PIN5_Msk (0x1 << DRV_SX1509_DATA_PIN5_Pos)
1049 #define DRV_SX1509_DATA_PIN5_Low (0)
1050 #define DRV_SX1509_DATA_PIN5_High (1)
1053 /* Field PIN4: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1054 #define DRV_SX1509_DATA_PIN4_Pos (4)
1055 #define DRV_SX1509_DATA_PIN4_Msk (0x1 << DRV_SX1509_DATA_PIN4_Pos)
1056 #define DRV_SX1509_DATA_PIN4_Low (0)
1057 #define DRV_SX1509_DATA_PIN4_High (1)
1060 /* Field PIN3: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1061 #define DRV_SX1509_DATA_PIN3_Pos (3)
1062 #define DRV_SX1509_DATA_PIN3_Msk (0x1 << DRV_SX1509_DATA_PIN3_Pos)
1063 #define DRV_SX1509_DATA_PIN3_Low (0)
1064 #define DRV_SX1509_DATA_PIN3_High (1)
1067 /* Field PIN2: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1068 #define DRV_SX1509_DATA_PIN2_Pos (2)
1069 #define DRV_SX1509_DATA_PIN2_Msk (0x1 << DRV_SX1509_DATA_PIN2_Pos)
1070 #define DRV_SX1509_DATA_PIN2_Low (0)
1071 #define DRV_SX1509_DATA_PIN2_High (1)
1074 /* Field PIN1: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1075 #define DRV_SX1509_DATA_PIN1_Pos (1)
1076 #define DRV_SX1509_DATA_PIN1_Msk (0x1 << DRV_SX1509_DATA_PIN1_Pos)
1077 #define DRV_SX1509_DATA_PIN1_Low (0)
1078 #define DRV_SX1509_DATA_PIN1_High (1)
1081 /* Field PIN0: Write: Data to be output to the output-configured IOs, Read: Data seen at the IOs, independent of the direction configured.. */
1082 #define DRV_SX1509_DATA_PIN0_Pos (0)
1083 #define DRV_SX1509_DATA_PIN0_Msk (0x1 << DRV_SX1509_DATA_PIN0_Pos)
1084 #define DRV_SX1509_DATA_PIN0_Low (0)
1085 #define DRV_SX1509_DATA_PIN0_High (1)
1088 /* Register: INTERRUPTMASK. */
1089 /* Description: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1090
1091
1092 /* Field PIN15: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1093 #define DRV_SX1509_INTERRUPTMASK_PIN15_Pos (15)
1094 #define DRV_SX1509_INTERRUPTMASK_PIN15_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN15_Pos)
1095 #define DRV_SX1509_INTERRUPTMASK_PIN15_Unmasked (0)
1096 #define DRV_SX1509_INTERRUPTMASK_PIN15_Masked (1)
1099 /* Field PIN14: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1100 #define DRV_SX1509_INTERRUPTMASK_PIN14_Pos (14)
1101 #define DRV_SX1509_INTERRUPTMASK_PIN14_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN14_Pos)
1102 #define DRV_SX1509_INTERRUPTMASK_PIN14_Unmasked (0)
1103 #define DRV_SX1509_INTERRUPTMASK_PIN14_Masked (1)
1106 /* Field PIN13: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1107 #define DRV_SX1509_INTERRUPTMASK_PIN13_Pos (13)
1108 #define DRV_SX1509_INTERRUPTMASK_PIN13_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN13_Pos)
1109 #define DRV_SX1509_INTERRUPTMASK_PIN13_Unmasked (0)
1110 #define DRV_SX1509_INTERRUPTMASK_PIN13_Masked (1)
1113 /* Field PIN12: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1114 #define DRV_SX1509_INTERRUPTMASK_PIN12_Pos (12)
1115 #define DRV_SX1509_INTERRUPTMASK_PIN12_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN12_Pos)
1116 #define DRV_SX1509_INTERRUPTMASK_PIN12_Unmasked (0)
1117 #define DRV_SX1509_INTERRUPTMASK_PIN12_Masked (1)
1120 /* Field PIN11: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1121 #define DRV_SX1509_INTERRUPTMASK_PIN11_Pos (11)
1122 #define DRV_SX1509_INTERRUPTMASK_PIN11_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN11_Pos)
1123 #define DRV_SX1509_INTERRUPTMASK_PIN11_Unmasked (0)
1124 #define DRV_SX1509_INTERRUPTMASK_PIN11_Masked (1)
1127 /* Field PIN10: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1128 #define DRV_SX1509_INTERRUPTMASK_PIN10_Pos (10)
1129 #define DRV_SX1509_INTERRUPTMASK_PIN10_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN10_Pos)
1130 #define DRV_SX1509_INTERRUPTMASK_PIN10_Unmasked (0)
1131 #define DRV_SX1509_INTERRUPTMASK_PIN10_Masked (1)
1134 /* Field PIN9: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1135 #define DRV_SX1509_INTERRUPTMASK_PIN9_Pos (9)
1136 #define DRV_SX1509_INTERRUPTMASK_PIN9_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN9_Pos)
1137 #define DRV_SX1509_INTERRUPTMASK_PIN9_Unmasked (0)
1138 #define DRV_SX1509_INTERRUPTMASK_PIN9_Masked (1)
1141 /* Field PIN8: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1142 #define DRV_SX1509_INTERRUPTMASK_PIN8_Pos (8)
1143 #define DRV_SX1509_INTERRUPTMASK_PIN8_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN8_Pos)
1144 #define DRV_SX1509_INTERRUPTMASK_PIN8_Unmasked (0)
1145 #define DRV_SX1509_INTERRUPTMASK_PIN8_Masked (1)
1148 /* Field PIN7: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1149 #define DRV_SX1509_INTERRUPTMASK_PIN7_Pos (7)
1150 #define DRV_SX1509_INTERRUPTMASK_PIN7_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN7_Pos)
1151 #define DRV_SX1509_INTERRUPTMASK_PIN7_Unmasked (0)
1152 #define DRV_SX1509_INTERRUPTMASK_PIN7_Masked (1)
1155 /* Field PIN6: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1156 #define DRV_SX1509_INTERRUPTMASK_PIN6_Pos (6)
1157 #define DRV_SX1509_INTERRUPTMASK_PIN6_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN6_Pos)
1158 #define DRV_SX1509_INTERRUPTMASK_PIN6_Unmasked (0)
1159 #define DRV_SX1509_INTERRUPTMASK_PIN6_Masked (1)
1162 /* Field PIN5: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1163 #define DRV_SX1509_INTERRUPTMASK_PIN5_Pos (5)
1164 #define DRV_SX1509_INTERRUPTMASK_PIN5_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN5_Pos)
1165 #define DRV_SX1509_INTERRUPTMASK_PIN5_Unmasked (0)
1166 #define DRV_SX1509_INTERRUPTMASK_PIN5_Masked (1)
1169 /* Field PIN4: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1170 #define DRV_SX1509_INTERRUPTMASK_PIN4_Pos (4)
1171 #define DRV_SX1509_INTERRUPTMASK_PIN4_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN4_Pos)
1172 #define DRV_SX1509_INTERRUPTMASK_PIN4_Unmasked (0)
1173 #define DRV_SX1509_INTERRUPTMASK_PIN4_Masked (1)
1176 /* Field PIN3: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1177 #define DRV_SX1509_INTERRUPTMASK_PIN3_Pos (3)
1178 #define DRV_SX1509_INTERRUPTMASK_PIN3_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN3_Pos)
1179 #define DRV_SX1509_INTERRUPTMASK_PIN3_Unmasked (0)
1180 #define DRV_SX1509_INTERRUPTMASK_PIN3_Masked (1)
1183 /* Field PIN2: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1184 #define DRV_SX1509_INTERRUPTMASK_PIN2_Pos (2)
1185 #define DRV_SX1509_INTERRUPTMASK_PIN2_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN2_Pos)
1186 #define DRV_SX1509_INTERRUPTMASK_PIN2_Unmasked (0)
1187 #define DRV_SX1509_INTERRUPTMASK_PIN2_Masked (1)
1190 /* Field PIN1: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1191 #define DRV_SX1509_INTERRUPTMASK_PIN1_Pos (1)
1192 #define DRV_SX1509_INTERRUPTMASK_PIN1_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN1_Pos)
1193 #define DRV_SX1509_INTERRUPTMASK_PIN1_Unmasked (0)
1194 #define DRV_SX1509_INTERRUPTMASK_PIN1_Masked (1)
1197 /* Field PIN0: Configures which [input-configured] IO will triggeran interrupt on NINT pin. */
1198 #define DRV_SX1509_INTERRUPTMASK_PIN0_Pos (0)
1199 #define DRV_SX1509_INTERRUPTMASK_PIN0_Msk (0x1 << DRV_SX1509_INTERRUPTMASK_PIN0_Pos)
1200 #define DRV_SX1509_INTERRUPTMASK_PIN0_Unmasked (0)
1201 #define DRV_SX1509_INTERRUPTMASK_PIN0_Masked (1)
1204 /* Register: SENSE. */
1205 /* Description: Configures edge sensitivity. */
1206
1207
1208 /* Field HIGH15: Configures the edge sensitivity of the corresponting RegData[n]. */
1209 #define DRV_SX1509_SENSE_HIGH15_Pos (30)
1210 #define DRV_SX1509_SENSE_HIGH15_Msk (0x3 << DRV_SX1509_SENSE_HIGH15_Pos)
1211 #define DRV_SX1509_SENSE_HIGH15_None (0)
1212 #define DRV_SX1509_SENSE_HIGH15_Rising (1)
1213 #define DRV_SX1509_SENSE_HIGH15_Falling (2)
1214 #define DRV_SX1509_SENSE_HIGH15_Both (3)
1217 /* Field HIGH14: Configures the edge sensitivity of the corresponting RegData[n]. */
1218 #define DRV_SX1509_SENSE_HIGH14_Pos (28)
1219 #define DRV_SX1509_SENSE_HIGH14_Msk (0x3 << DRV_SX1509_SENSE_HIGH14_Pos)
1220 #define DRV_SX1509_SENSE_HIGH14_None (0)
1221 #define DRV_SX1509_SENSE_HIGH14_Rising (1)
1222 #define DRV_SX1509_SENSE_HIGH14_Falling (2)
1223 #define DRV_SX1509_SENSE_HIGH14_Both (3)
1226 /* Field HIGH13: Configures the edge sensitivity of the corresponting RegData[n]. */
1227 #define DRV_SX1509_SENSE_HIGH13_Pos (26)
1228 #define DRV_SX1509_SENSE_HIGH13_Msk (0x3 << DRV_SX1509_SENSE_HIGH13_Pos)
1229 #define DRV_SX1509_SENSE_HIGH13_None (0)
1230 #define DRV_SX1509_SENSE_HIGH13_Rising (1)
1231 #define DRV_SX1509_SENSE_HIGH13_Falling (2)
1232 #define DRV_SX1509_SENSE_HIGH13_Both (3)
1235 /* Field HIGH12: Configures the edge sensitivity of the corresponting RegData[n]. */
1236 #define DRV_SX1509_SENSE_HIGH12_Pos (24)
1237 #define DRV_SX1509_SENSE_HIGH12_Msk (0x3 << DRV_SX1509_SENSE_HIGH12_Pos)
1238 #define DRV_SX1509_SENSE_HIGH12_None (0)
1239 #define DRV_SX1509_SENSE_HIGH12_Rising (1)
1240 #define DRV_SX1509_SENSE_HIGH12_Falling (2)
1241 #define DRV_SX1509_SENSE_HIGH12_Both (3)
1244 /* Field LOW11: Configures the edge sensitivity of the corresponting RegData[n]. */
1245 #define DRV_SX1509_SENSE_LOW11_Pos (22)
1246 #define DRV_SX1509_SENSE_LOW11_Msk (0x3 << DRV_SX1509_SENSE_LOW11_Pos)
1247 #define DRV_SX1509_SENSE_LOW11_None (0)
1248 #define DRV_SX1509_SENSE_LOW11_Rising (1)
1249 #define DRV_SX1509_SENSE_LOW11_Falling (2)
1250 #define DRV_SX1509_SENSE_LOW11_Both (3)
1253 /* Field LOW10: Configures the edge sensitivity of the corresponting RegData[n]. */
1254 #define DRV_SX1509_SENSE_LOW10_Pos (20)
1255 #define DRV_SX1509_SENSE_LOW10_Msk (0x3 << DRV_SX1509_SENSE_LOW10_Pos)
1256 #define DRV_SX1509_SENSE_LOW10_None (0)
1257 #define DRV_SX1509_SENSE_LOW10_Rising (1)
1258 #define DRV_SX1509_SENSE_LOW10_Falling (2)
1259 #define DRV_SX1509_SENSE_LOW10_Both (3)
1262 /* Field LOW9: Configures the edge sensitivity of the corresponting RegData[n]. */
1263 #define DRV_SX1509_SENSE_LOW9_Pos (18)
1264 #define DRV_SX1509_SENSE_LOW9_Msk (0x3 << DRV_SX1509_SENSE_LOW9_Pos)
1265 #define DRV_SX1509_SENSE_LOW9_None (0)
1266 #define DRV_SX1509_SENSE_LOW9_Rising (1)
1267 #define DRV_SX1509_SENSE_LOW9_Falling (2)
1268 #define DRV_SX1509_SENSE_LOW9_Both (3)
1271 /* Field LOW8: Configures the edge sensitivity of the corresponting RegData[n]. */
1272 #define DRV_SX1509_SENSE_LOW8_Pos (16)
1273 #define DRV_SX1509_SENSE_LOW8_Msk (0x3 << DRV_SX1509_SENSE_LOW8_Pos)
1274 #define DRV_SX1509_SENSE_LOW8_None (0)
1275 #define DRV_SX1509_SENSE_LOW8_Rising (1)
1276 #define DRV_SX1509_SENSE_LOW8_Falling (2)
1277 #define DRV_SX1509_SENSE_LOW8_Both (3)
1280 /* Field HIGH7: Configures the edge sensitivity of the corresponting RegData[n]. */
1281 #define DRV_SX1509_SENSE_HIGH7_Pos (14)
1282 #define DRV_SX1509_SENSE_HIGH7_Msk (0x3 << DRV_SX1509_SENSE_HIGH7_Pos)
1283 #define DRV_SX1509_SENSE_HIGH7_None (0)
1284 #define DRV_SX1509_SENSE_HIGH7_Rising (1)
1285 #define DRV_SX1509_SENSE_HIGH7_Falling (2)
1286 #define DRV_SX1509_SENSE_HIGH7_Both (3)
1289 /* Field HIGH6: Configures the edge sensitivity of the corresponting RegData[n]. */
1290 #define DRV_SX1509_SENSE_HIGH6_Pos (12)
1291 #define DRV_SX1509_SENSE_HIGH6_Msk (0x3 << DRV_SX1509_SENSE_HIGH6_Pos)
1292 #define DRV_SX1509_SENSE_HIGH6_None (0)
1293 #define DRV_SX1509_SENSE_HIGH6_Rising (1)
1294 #define DRV_SX1509_SENSE_HIGH6_Falling (2)
1295 #define DRV_SX1509_SENSE_HIGH6_Both (3)
1298 /* Field HIGH5: Configures the edge sensitivity of the corresponting RegData[n]. */
1299 #define DRV_SX1509_SENSE_HIGH5_Pos (10)
1300 #define DRV_SX1509_SENSE_HIGH5_Msk (0x3 << DRV_SX1509_SENSE_HIGH5_Pos)
1301 #define DRV_SX1509_SENSE_HIGH5_None (0)
1302 #define DRV_SX1509_SENSE_HIGH5_Rising (1)
1303 #define DRV_SX1509_SENSE_HIGH5_Falling (2)
1304 #define DRV_SX1509_SENSE_HIGH5_Both (3)
1307 /* Field HIGH4: Configures the edge sensitivity of the corresponting RegData[n]. */
1308 #define DRV_SX1509_SENSE_HIGH4_Pos (8)
1309 #define DRV_SX1509_SENSE_HIGH4_Msk (0x3 << DRV_SX1509_SENSE_HIGH4_Pos)
1310 #define DRV_SX1509_SENSE_HIGH4_None (0)
1311 #define DRV_SX1509_SENSE_HIGH4_Rising (1)
1312 #define DRV_SX1509_SENSE_HIGH4_Falling (2)
1313 #define DRV_SX1509_SENSE_HIGH4_Both (3)
1316 /* Field LOW3: Configures the edge sensitivity of the corresponting RegData[n]. */
1317 #define DRV_SX1509_SENSE_LOW3_Pos (6)
1318 #define DRV_SX1509_SENSE_LOW3_Msk (0x3 << DRV_SX1509_SENSE_LOW3_Pos)
1319 #define DRV_SX1509_SENSE_LOW3_None (0)
1320 #define DRV_SX1509_SENSE_LOW3_Rising (1)
1321 #define DRV_SX1509_SENSE_LOW3_Falling (2)
1322 #define DRV_SX1509_SENSE_LOW3_Both (3)
1325 /* Field LOW2: Configures the edge sensitivity of the corresponting RegData[n]. */
1326 #define DRV_SX1509_SENSE_LOW2_Pos (4)
1327 #define DRV_SX1509_SENSE_LOW2_Msk (0x3 << DRV_SX1509_SENSE_LOW2_Pos)
1328 #define DRV_SX1509_SENSE_LOW2_None (0)
1329 #define DRV_SX1509_SENSE_LOW2_Rising (1)
1330 #define DRV_SX1509_SENSE_LOW2_Falling (2)
1331 #define DRV_SX1509_SENSE_LOW2_Both (3)
1334 /* Field LOW1: Configures the edge sensitivity of the corresponting RegData[n]. */
1335 #define DRV_SX1509_SENSE_LOW1_Pos (2)
1336 #define DRV_SX1509_SENSE_LOW1_Msk (0x3 << DRV_SX1509_SENSE_LOW1_Pos)
1337 #define DRV_SX1509_SENSE_LOW1_None (0)
1338 #define DRV_SX1509_SENSE_LOW1_Rising (1)
1339 #define DRV_SX1509_SENSE_LOW1_Falling (2)
1340 #define DRV_SX1509_SENSE_LOW1_Both (3)
1343 /* Field LOW0: Configures the edge sensitivity of the corresponting RegData[n]. */
1344 #define DRV_SX1509_SENSE_LOW0_Pos (0)
1345 #define DRV_SX1509_SENSE_LOW0_Msk (0x3 << DRV_SX1509_SENSE_LOW0_Pos)
1346 #define DRV_SX1509_SENSE_LOW0_None (0)
1347 #define DRV_SX1509_SENSE_LOW0_Rising (1)
1348 #define DRV_SX1509_SENSE_LOW0_Falling (2)
1349 #define DRV_SX1509_SENSE_LOW0_Both (3)
1352 /* Register: INTERRUPTSOURCE. */
1353 /* Description: Interrupt source register - I/O. */
1354
1355
1356 /* Field PIN15: Interrupt source (from IOs set in RegInterruptMask). */
1357 #define DRV_SX1509_INTERRUPTSOURCE_PIN15_Pos (15)
1358 #define DRV_SX1509_INTERRUPTSOURCE_PIN15_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN15_Pos)
1359 #define DRV_SX1509_INTERRUPTSOURCE_PIN15_None (0)
1360 #define DRV_SX1509_INTERRUPTSOURCE_PIN15_Triggered (1)
1363 /* Field PIN14: Interrupt source (from IOs set in RegInterruptMask). */
1364 #define DRV_SX1509_INTERRUPTSOURCE_PIN14_Pos (14)
1365 #define DRV_SX1509_INTERRUPTSOURCE_PIN14_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN14_Pos)
1366 #define DRV_SX1509_INTERRUPTSOURCE_PIN14_None (0)
1367 #define DRV_SX1509_INTERRUPTSOURCE_PIN14_Triggered (1)
1370 /* Field PIN13: Interrupt source (from IOs set in RegInterruptMask). */
1371 #define DRV_SX1509_INTERRUPTSOURCE_PIN13_Pos (13)
1372 #define DRV_SX1509_INTERRUPTSOURCE_PIN13_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN13_Pos)
1373 #define DRV_SX1509_INTERRUPTSOURCE_PIN13_None (0)
1374 #define DRV_SX1509_INTERRUPTSOURCE_PIN13_Triggered (1)
1377 /* Field PIN12: Interrupt source (from IOs set in RegInterruptMask). */
1378 #define DRV_SX1509_INTERRUPTSOURCE_PIN12_Pos (12)
1379 #define DRV_SX1509_INTERRUPTSOURCE_PIN12_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN12_Pos)
1380 #define DRV_SX1509_INTERRUPTSOURCE_PIN12_None (0)
1381 #define DRV_SX1509_INTERRUPTSOURCE_PIN12_Triggered (1)
1384 /* Field PIN11: Interrupt source (from IOs set in RegInterruptMask). */
1385 #define DRV_SX1509_INTERRUPTSOURCE_PIN11_Pos (11)
1386 #define DRV_SX1509_INTERRUPTSOURCE_PIN11_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN11_Pos)
1387 #define DRV_SX1509_INTERRUPTSOURCE_PIN11_None (0)
1388 #define DRV_SX1509_INTERRUPTSOURCE_PIN11_Triggered (1)
1391 /* Field PIN10: Interrupt source (from IOs set in RegInterruptMask). */
1392 #define DRV_SX1509_INTERRUPTSOURCE_PIN10_Pos (10)
1393 #define DRV_SX1509_INTERRUPTSOURCE_PIN10_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN10_Pos)
1394 #define DRV_SX1509_INTERRUPTSOURCE_PIN10_None (0)
1395 #define DRV_SX1509_INTERRUPTSOURCE_PIN10_Triggered (1)
1398 /* Field PIN9: Interrupt source (from IOs set in RegInterruptMask). */
1399 #define DRV_SX1509_INTERRUPTSOURCE_PIN9_Pos (9)
1400 #define DRV_SX1509_INTERRUPTSOURCE_PIN9_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN9_Pos)
1401 #define DRV_SX1509_INTERRUPTSOURCE_PIN9_None (0)
1402 #define DRV_SX1509_INTERRUPTSOURCE_PIN9_Triggered (1)
1405 /* Field PIN8: Interrupt source (from IOs set in RegInterruptMask). */
1406 #define DRV_SX1509_INTERRUPTSOURCE_PIN8_Pos (8)
1407 #define DRV_SX1509_INTERRUPTSOURCE_PIN8_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN8_Pos)
1408 #define DRV_SX1509_INTERRUPTSOURCE_PIN8_None (0)
1409 #define DRV_SX1509_INTERRUPTSOURCE_PIN8_Triggered (1)
1412 /* Field PIN7: Interrupt source (from IOs set in RegInterruptMask). */
1413 #define DRV_SX1509_INTERRUPTSOURCE_PIN7_Pos (7)
1414 #define DRV_SX1509_INTERRUPTSOURCE_PIN7_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN7_Pos)
1415 #define DRV_SX1509_INTERRUPTSOURCE_PIN7_None (0)
1416 #define DRV_SX1509_INTERRUPTSOURCE_PIN7_Triggered (1)
1419 /* Field PIN6: Interrupt source (from IOs set in RegInterruptMask). */
1420 #define DRV_SX1509_INTERRUPTSOURCE_PIN6_Pos (6)
1421 #define DRV_SX1509_INTERRUPTSOURCE_PIN6_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN6_Pos)
1422 #define DRV_SX1509_INTERRUPTSOURCE_PIN6_None (0)
1423 #define DRV_SX1509_INTERRUPTSOURCE_PIN6_Triggered (1)
1426 /* Field PIN5: Interrupt source (from IOs set in RegInterruptMask). */
1427 #define DRV_SX1509_INTERRUPTSOURCE_PIN5_Pos (5)
1428 #define DRV_SX1509_INTERRUPTSOURCE_PIN5_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN5_Pos)
1429 #define DRV_SX1509_INTERRUPTSOURCE_PIN5_None (0)
1430 #define DRV_SX1509_INTERRUPTSOURCE_PIN5_Triggered (1)
1433 /* Field PIN4: Interrupt source (from IOs set in RegInterruptMask). */
1434 #define DRV_SX1509_INTERRUPTSOURCE_PIN4_Pos (4)
1435 #define DRV_SX1509_INTERRUPTSOURCE_PIN4_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN4_Pos)
1436 #define DRV_SX1509_INTERRUPTSOURCE_PIN4_None (0)
1437 #define DRV_SX1509_INTERRUPTSOURCE_PIN4_Triggered (1)
1440 /* Field PIN3: Interrupt source (from IOs set in RegInterruptMask). */
1441 #define DRV_SX1509_INTERRUPTSOURCE_PIN3_Pos (3)
1442 #define DRV_SX1509_INTERRUPTSOURCE_PIN3_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN3_Pos)
1443 #define DRV_SX1509_INTERRUPTSOURCE_PIN3_None (0)
1444 #define DRV_SX1509_INTERRUPTSOURCE_PIN3_Triggered (1)
1447 /* Field PIN2: Interrupt source (from IOs set in RegInterruptMask). */
1448 #define DRV_SX1509_INTERRUPTSOURCE_PIN2_Pos (2)
1449 #define DRV_SX1509_INTERRUPTSOURCE_PIN2_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN2_Pos)
1450 #define DRV_SX1509_INTERRUPTSOURCE_PIN2_None (0)
1451 #define DRV_SX1509_INTERRUPTSOURCE_PIN2_Triggered (1)
1454 /* Field PIN1: Interrupt source (from IOs set in RegInterruptMask). */
1455 #define DRV_SX1509_INTERRUPTSOURCE_PIN1_Pos (1)
1456 #define DRV_SX1509_INTERRUPTSOURCE_PIN1_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN1_Pos)
1457 #define DRV_SX1509_INTERRUPTSOURCE_PIN1_None (0)
1458 #define DRV_SX1509_INTERRUPTSOURCE_PIN1_Triggered (1)
1461 /* Field PIN0: Interrupt source (from IOs set in RegInterruptMask). */
1462 #define DRV_SX1509_INTERRUPTSOURCE_PIN0_Pos (0)
1463 #define DRV_SX1509_INTERRUPTSOURCE_PIN0_Msk (0x1 << DRV_SX1509_INTERRUPTSOURCE_PIN0_Pos)
1464 #define DRV_SX1509_INTERRUPTSOURCE_PIN0_None (0)
1465 #define DRV_SX1509_INTERRUPTSOURCE_PIN0_Triggered (1)
1468 /* Register: EVENTSTATUS. */
1469 /* Description: Event status register - I/O. */
1470
1471
1472 /* Field PIN15: Interrupt source (from IOs set in RegInterruptMask). */
1473 #define DRV_SX1509_EVENTSTATUS_PIN15_Pos (15)
1474 #define DRV_SX1509_EVENTSTATUS_PIN15_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN15_Pos)
1475 #define DRV_SX1509_EVENTSTATUS_PIN15_None (0)
1476 #define DRV_SX1509_EVENTSTATUS_PIN15_Triggered (1)
1479 /* Field PIN14: Interrupt source (from IOs set in RegInterruptMask). */
1480 #define DRV_SX1509_EVENTSTATUS_PIN14_Pos (14)
1481 #define DRV_SX1509_EVENTSTATUS_PIN14_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN14_Pos)
1482 #define DRV_SX1509_EVENTSTATUS_PIN14_None (0)
1483 #define DRV_SX1509_EVENTSTATUS_PIN14_Triggered (1)
1486 /* Field PIN13: Interrupt source (from IOs set in RegInterruptMask). */
1487 #define DRV_SX1509_EVENTSTATUS_PIN13_Pos (13)
1488 #define DRV_SX1509_EVENTSTATUS_PIN13_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN13_Pos)
1489 #define DRV_SX1509_EVENTSTATUS_PIN13_None (0)
1490 #define DRV_SX1509_EVENTSTATUS_PIN13_Triggered (1)
1493 /* Field PIN12: Interrupt source (from IOs set in RegInterruptMask). */
1494 #define DRV_SX1509_EVENTSTATUS_PIN12_Pos (12)
1495 #define DRV_SX1509_EVENTSTATUS_PIN12_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN12_Pos)
1496 #define DRV_SX1509_EVENTSTATUS_PIN12_None (0)
1497 #define DRV_SX1509_EVENTSTATUS_PIN12_Triggered (1)
1500 /* Field PIN11: Interrupt source (from IOs set in RegInterruptMask). */
1501 #define DRV_SX1509_EVENTSTATUS_PIN11_Pos (11)
1502 #define DRV_SX1509_EVENTSTATUS_PIN11_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN11_Pos)
1503 #define DRV_SX1509_EVENTSTATUS_PIN11_None (0)
1504 #define DRV_SX1509_EVENTSTATUS_PIN11_Triggered (1)
1507 /* Field PIN10: Interrupt source (from IOs set in RegInterruptMask). */
1508 #define DRV_SX1509_EVENTSTATUS_PIN10_Pos (10)
1509 #define DRV_SX1509_EVENTSTATUS_PIN10_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN10_Pos)
1510 #define DRV_SX1509_EVENTSTATUS_PIN10_None (0)
1511 #define DRV_SX1509_EVENTSTATUS_PIN10_Triggered (1)
1514 /* Field PIN9: Interrupt source (from IOs set in RegInterruptMask). */
1515 #define DRV_SX1509_EVENTSTATUS_PIN9_Pos (9)
1516 #define DRV_SX1509_EVENTSTATUS_PIN9_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN9_Pos)
1517 #define DRV_SX1509_EVENTSTATUS_PIN9_None (0)
1518 #define DRV_SX1509_EVENTSTATUS_PIN9_Triggered (1)
1521 /* Field PIN8: Interrupt source (from IOs set in RegInterruptMask). */
1522 #define DRV_SX1509_EVENTSTATUS_PIN8_Pos (8)
1523 #define DRV_SX1509_EVENTSTATUS_PIN8_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN8_Pos)
1524 #define DRV_SX1509_EVENTSTATUS_PIN8_None (0)
1525 #define DRV_SX1509_EVENTSTATUS_PIN8_Triggered (1)
1528 /* Field PIN7: Interrupt source (from IOs set in RegInterruptMask). */
1529 #define DRV_SX1509_EVENTSTATUS_PIN7_Pos (7)
1530 #define DRV_SX1509_EVENTSTATUS_PIN7_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN7_Pos)
1531 #define DRV_SX1509_EVENTSTATUS_PIN7_None (0)
1532 #define DRV_SX1509_EVENTSTATUS_PIN7_Triggered (1)
1535 /* Field PIN6: Interrupt source (from IOs set in RegInterruptMask). */
1536 #define DRV_SX1509_EVENTSTATUS_PIN6_Pos (6)
1537 #define DRV_SX1509_EVENTSTATUS_PIN6_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN6_Pos)
1538 #define DRV_SX1509_EVENTSTATUS_PIN6_None (0)
1539 #define DRV_SX1509_EVENTSTATUS_PIN6_Triggered (1)
1542 /* Field PIN5: Interrupt source (from IOs set in RegInterruptMask). */
1543 #define DRV_SX1509_EVENTSTATUS_PIN5_Pos (5)
1544 #define DRV_SX1509_EVENTSTATUS_PIN5_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN5_Pos)
1545 #define DRV_SX1509_EVENTSTATUS_PIN5_None (0)
1546 #define DRV_SX1509_EVENTSTATUS_PIN5_Triggered (1)
1549 /* Field PIN4: Interrupt source (from IOs set in RegInterruptMask). */
1550 #define DRV_SX1509_EVENTSTATUS_PIN4_Pos (4)
1551 #define DRV_SX1509_EVENTSTATUS_PIN4_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN4_Pos)
1552 #define DRV_SX1509_EVENTSTATUS_PIN4_None (0)
1553 #define DRV_SX1509_EVENTSTATUS_PIN4_Triggered (1)
1556 /* Field PIN3: Interrupt source (from IOs set in RegInterruptMask). */
1557 #define DRV_SX1509_EVENTSTATUS_PIN3_Pos (3)
1558 #define DRV_SX1509_EVENTSTATUS_PIN3_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN3_Pos)
1559 #define DRV_SX1509_EVENTSTATUS_PIN3_None (0)
1560 #define DRV_SX1509_EVENTSTATUS_PIN3_Triggered (1)
1563 /* Field PIN2: Interrupt source (from IOs set in RegInterruptMask). */
1564 #define DRV_SX1509_EVENTSTATUS_PIN2_Pos (2)
1565 #define DRV_SX1509_EVENTSTATUS_PIN2_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN2_Pos)
1566 #define DRV_SX1509_EVENTSTATUS_PIN2_None (0)
1567 #define DRV_SX1509_EVENTSTATUS_PIN2_Triggered (1)
1570 /* Field PIN1: Interrupt source (from IOs set in RegInterruptMask). */
1571 #define DRV_SX1509_EVENTSTATUS_PIN1_Pos (1)
1572 #define DRV_SX1509_EVENTSTATUS_PIN1_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN1_Pos)
1573 #define DRV_SX1509_EVENTSTATUS_PIN1_None (0)
1574 #define DRV_SX1509_EVENTSTATUS_PIN1_Triggered (1)
1577 /* Field PIN0: Interrupt source (from IOs set in RegInterruptMask). */
1578 #define DRV_SX1509_EVENTSTATUS_PIN0_Pos (0)
1579 #define DRV_SX1509_EVENTSTATUS_PIN0_Msk (0x1 << DRV_SX1509_EVENTSTATUS_PIN0_Pos)
1580 #define DRV_SX1509_EVENTSTATUS_PIN0_None (0)
1581 #define DRV_SX1509_EVENTSTATUS_PIN0_Triggered (1)
1584 /* Register: LEVELSHIFTER. */
1585 /* Description: Level shifter register. */
1586
1587
1588 /* Field MODE7: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1589 #define DRV_SX1509_LEVELSHIFTER_MODE7_Pos (14)
1590 #define DRV_SX1509_LEVELSHIFTER_MODE7_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE7_Pos)
1591 #define DRV_SX1509_LEVELSHIFTER_MODE7_Off (0)
1592 #define DRV_SX1509_LEVELSHIFTER_MODE7_AB (1)
1593 #define DRV_SX1509_LEVELSHIFTER_MODE7_BA (2)
1596 /* Field MODE6: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1597 #define DRV_SX1509_LEVELSHIFTER_MODE6_Pos (12)
1598 #define DRV_SX1509_LEVELSHIFTER_MODE6_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE6_Pos)
1599 #define DRV_SX1509_LEVELSHIFTER_MODE6_Off (0)
1600 #define DRV_SX1509_LEVELSHIFTER_MODE6_AB (1)
1601 #define DRV_SX1509_LEVELSHIFTER_MODE6_BA (2)
1604 /* Field MODE5: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1605 #define DRV_SX1509_LEVELSHIFTER_MODE5_Pos (10)
1606 #define DRV_SX1509_LEVELSHIFTER_MODE5_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE5_Pos)
1607 #define DRV_SX1509_LEVELSHIFTER_MODE5_Off (0)
1608 #define DRV_SX1509_LEVELSHIFTER_MODE5_AB (1)
1609 #define DRV_SX1509_LEVELSHIFTER_MODE5_BA (2)
1612 /* Field MODE4: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1613 #define DRV_SX1509_LEVELSHIFTER_MODE4_Pos (8)
1614 #define DRV_SX1509_LEVELSHIFTER_MODE4_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE4_Pos)
1615 #define DRV_SX1509_LEVELSHIFTER_MODE4_Off (0)
1616 #define DRV_SX1509_LEVELSHIFTER_MODE4_AB (1)
1617 #define DRV_SX1509_LEVELSHIFTER_MODE4_BA (2)
1620 /* Field MODE3: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1621 #define DRV_SX1509_LEVELSHIFTER_MODE3_Pos (6)
1622 #define DRV_SX1509_LEVELSHIFTER_MODE3_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE3_Pos)
1623 #define DRV_SX1509_LEVELSHIFTER_MODE3_Off (0)
1624 #define DRV_SX1509_LEVELSHIFTER_MODE3_AB (1)
1625 #define DRV_SX1509_LEVELSHIFTER_MODE3_BA (2)
1628 /* Field MODE2: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1629 #define DRV_SX1509_LEVELSHIFTER_MODE2_Pos (4)
1630 #define DRV_SX1509_LEVELSHIFTER_MODE2_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE2_Pos)
1631 #define DRV_SX1509_LEVELSHIFTER_MODE2_Off (0)
1632 #define DRV_SX1509_LEVELSHIFTER_MODE2_AB (1)
1633 #define DRV_SX1509_LEVELSHIFTER_MODE2_BA (2)
1636 /* Field MODE1: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1637 #define DRV_SX1509_LEVELSHIFTER_MODE1_Pos (2)
1638 #define DRV_SX1509_LEVELSHIFTER_MODE1_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE1_Pos)
1639 #define DRV_SX1509_LEVELSHIFTER_MODE1_Off (0)
1640 #define DRV_SX1509_LEVELSHIFTER_MODE1_AB (1)
1641 #define DRV_SX1509_LEVELSHIFTER_MODE1_BA (2)
1644 /* Field MODE0: Level shifter mode for IO[n] (Bank A) and IO[8 + n] (Bank B). */
1645 #define DRV_SX1509_LEVELSHIFTER_MODE0_Pos (0)
1646 #define DRV_SX1509_LEVELSHIFTER_MODE0_Msk (0x3 << DRV_SX1509_LEVELSHIFTER_MODE0_Pos)
1647 #define DRV_SX1509_LEVELSHIFTER_MODE0_Off (0)
1648 #define DRV_SX1509_LEVELSHIFTER_MODE0_AB (1)
1649 #define DRV_SX1509_LEVELSHIFTER_MODE0_BA (2)
1652 /* Register: CLOCK. */
1653 /* Description: Clock management register. */
1654
1655
1656 /* Field RESERVED0: Unused field. */
1657 #define DRV_SX1509_CLOCK_RESERVED0_Pos (7)
1658 #define DRV_SX1509_CLOCK_RESERVED0_Msk (0x1 << DRV_SX1509_CLOCK_RESERVED0_Pos)
1661 /* Field FOSCSRC: Oscillator frequency (fOSC) source. */
1662 #define DRV_SX1509_CLOCK_FOSCSRC_Pos (5)
1663 #define DRV_SX1509_CLOCK_FOSCSRC_Msk (0x3 << DRV_SX1509_CLOCK_FOSCSRC_Pos)
1664 #define DRV_SX1509_CLOCK_FOSCSRC_Off (0)
1665 #define DRV_SX1509_CLOCK_FOSCSRC_OscIn (1)
1666 #define DRV_SX1509_CLOCK_FOSCSRC_Int2MHz (2)
1669 /* Field OSCIODIR: OSCIO pin function (Cf. �4.8). */
1670 #define DRV_SX1509_CLOCK_OSCIODIR_Pos (4)
1671 #define DRV_SX1509_CLOCK_OSCIODIR_Msk (0x1 << DRV_SX1509_CLOCK_OSCIODIR_Pos)
1672 #define DRV_SX1509_CLOCK_OSCIODIR_Input (0)
1673 #define DRV_SX1509_CLOCK_OSCIODIR_Output (1)
1676 /* Field FREQ: Frequency of the signal output on OSCOUT pin, fOSCOUT = fOSC/(2^(RegClock[3:0]-1)). */
1677 #define DRV_SX1509_CLOCK_FREQ_Pos (0)
1678 #define DRV_SX1509_CLOCK_FREQ_Msk (0xF << DRV_SX1509_CLOCK_FREQ_Pos)
1679 #define DRV_SX1509_CLOCK_FREQ_Lo0Hz (0)
1680 #define DRV_SX1509_CLOCK_FREQ_Hi0Hz (1)
1683 /* Register: MISC. */
1684 /* Description: Miscellaneous device settings register. */
1685
1686
1687 /* Field MODE: LED Driver mode for Bank B's fading capable IOs (IO15-12). */
1688 #define DRV_SX1509_MISC_MODE_Pos (7)
1689 #define DRV_SX1509_MISC_MODE_Msk (0x1 << DRV_SX1509_MISC_MODE_Pos)
1690 #define DRV_SX1509_MISC_MODE_Linear (0)
1691 #define DRV_SX1509_MISC_MODE_Logarithmic (1)
1694 /* Field CLKX: Frequency of the LED Driver clock ClkX of all IOs. */
1695 #define DRV_SX1509_MISC_CLKX_Pos (4)
1696 #define DRV_SX1509_MISC_CLKX_Msk (0x7 << DRV_SX1509_MISC_CLKX_Pos)
1697 #define DRV_SX1509_MISC_CLKX_Off (0)
1700 /* Field DRVMODE: LED Driver mode for Bank A @s fading capable IOs (IO7-4). */
1701 #define DRV_SX1509_MISC_DRVMODE_Pos (3)
1702 #define DRV_SX1509_MISC_DRVMODE_Msk (0x1 << DRV_SX1509_MISC_DRVMODE_Pos)
1703 #define DRV_SX1509_MISC_DRVMODE_Linear (0)
1704 #define DRV_SX1509_MISC_DRVMODE_Logarithmic (1)
1707 /* Field FUNC: NRESET pin function when externally forced low (Cf. �4.4.1 and �4.9.5). */
1708 #define DRV_SX1509_MISC_FUNC_Pos (2)
1709 #define DRV_SX1509_MISC_FUNC_Msk (0x1 << DRV_SX1509_MISC_FUNC_Pos)
1710 #define DRV_SX1509_MISC_FUNC_EqPOR (0)
1711 #define DRV_SX1509_MISC_FUNC_Lmited (1)
1714 /* Field AUTOINC: Auto-increment register address (Cf. �4.5). */
1715 #define DRV_SX1509_MISC_AUTOINC_Pos (1)
1716 #define DRV_SX1509_MISC_AUTOINC_Msk (0x1 << DRV_SX1509_MISC_AUTOINC_Pos)
1717 #define DRV_SX1509_MISC_AUTOINC_On (0)
1718 #define DRV_SX1509_MISC_AUTOINC_Off (1)
1721 /* Field AUTOCLR: Autoclear NINT on RegData read (Cf. �4.7). */
1722 #define DRV_SX1509_MISC_AUTOCLR_Pos (0)
1723 #define DRV_SX1509_MISC_AUTOCLR_Msk (0x1 << DRV_SX1509_MISC_AUTOCLR_Pos)
1724 #define DRV_SX1509_MISC_AUTOCLR_On (0)
1725 #define DRV_SX1509_MISC_AUTOCLR_Off (1)
1728 /* Register: LEDDRIVERENABLE. */
1729 /* Description: LED driver enable register - I/O[n]. */
1730
1731
1732 /* Field PIN15: Enables LED Driver for each [output-configured] IO. */
1733 #define DRV_SX1509_LEDDRIVERENABLE_PIN15_Pos (15)
1734 #define DRV_SX1509_LEDDRIVERENABLE_PIN15_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN15_Pos)
1735 #define DRV_SX1509_LEDDRIVERENABLE_PIN15_Disabled (0)
1736 #define DRV_SX1509_LEDDRIVERENABLE_PIN15_Enabled (1)
1739 /* Field PIN14: Enables LED Driver for each [output-configured] IO. */
1740 #define DRV_SX1509_LEDDRIVERENABLE_PIN14_Pos (14)
1741 #define DRV_SX1509_LEDDRIVERENABLE_PIN14_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN14_Pos)
1742 #define DRV_SX1509_LEDDRIVERENABLE_PIN14_Disabled (0)
1743 #define DRV_SX1509_LEDDRIVERENABLE_PIN14_Enabled (1)
1746 /* Field PIN13: Enables LED Driver for each [output-configured] IO. */
1747 #define DRV_SX1509_LEDDRIVERENABLE_PIN13_Pos (13)
1748 #define DRV_SX1509_LEDDRIVERENABLE_PIN13_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN13_Pos)
1749 #define DRV_SX1509_LEDDRIVERENABLE_PIN13_Disabled (0)
1750 #define DRV_SX1509_LEDDRIVERENABLE_PIN13_Enabled (1)
1753 /* Field PIN12: Enables LED Driver for each [output-configured] IO. */
1754 #define DRV_SX1509_LEDDRIVERENABLE_PIN12_Pos (12)
1755 #define DRV_SX1509_LEDDRIVERENABLE_PIN12_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN12_Pos)
1756 #define DRV_SX1509_LEDDRIVERENABLE_PIN12_Disabled (0)
1757 #define DRV_SX1509_LEDDRIVERENABLE_PIN12_Enabled (1)
1760 /* Field PIN11: Enables LED Driver for each [output-configured] IO. */
1761 #define DRV_SX1509_LEDDRIVERENABLE_PIN11_Pos (11)
1762 #define DRV_SX1509_LEDDRIVERENABLE_PIN11_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN11_Pos)
1763 #define DRV_SX1509_LEDDRIVERENABLE_PIN11_Disabled (0)
1764 #define DRV_SX1509_LEDDRIVERENABLE_PIN11_Enabled (1)
1767 /* Field PIN10: Enables LED Driver for each [output-configured] IO. */
1768 #define DRV_SX1509_LEDDRIVERENABLE_PIN10_Pos (10)
1769 #define DRV_SX1509_LEDDRIVERENABLE_PIN10_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN10_Pos)
1770 #define DRV_SX1509_LEDDRIVERENABLE_PIN10_Disabled (0)
1771 #define DRV_SX1509_LEDDRIVERENABLE_PIN10_Enabled (1)
1774 /* Field PIN9: Enables LED Driver for each [output-configured] IO. */
1775 #define DRV_SX1509_LEDDRIVERENABLE_PIN9_Pos (9)
1776 #define DRV_SX1509_LEDDRIVERENABLE_PIN9_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN9_Pos)
1777 #define DRV_SX1509_LEDDRIVERENABLE_PIN9_Disabled (0)
1778 #define DRV_SX1509_LEDDRIVERENABLE_PIN9_Enabled (1)
1781 /* Field PIN8: Enables LED Driver for each [output-configured] IO. */
1782 #define DRV_SX1509_LEDDRIVERENABLE_PIN8_Pos (8)
1783 #define DRV_SX1509_LEDDRIVERENABLE_PIN8_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN8_Pos)
1784 #define DRV_SX1509_LEDDRIVERENABLE_PIN8_Disabled (0)
1785 #define DRV_SX1509_LEDDRIVERENABLE_PIN8_Enabled (1)
1788 /* Field PIN7: Enables LED Driver for each [output-configured] IO. */
1789 #define DRV_SX1509_LEDDRIVERENABLE_PIN7_Pos (7)
1790 #define DRV_SX1509_LEDDRIVERENABLE_PIN7_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN7_Pos)
1791 #define DRV_SX1509_LEDDRIVERENABLE_PIN7_Disabled (0)
1792 #define DRV_SX1509_LEDDRIVERENABLE_PIN7_Enabled (1)
1795 /* Field PIN6: Enables LED Driver for each [output-configured] IO. */
1796 #define DRV_SX1509_LEDDRIVERENABLE_PIN6_Pos (6)
1797 #define DRV_SX1509_LEDDRIVERENABLE_PIN6_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN6_Pos)
1798 #define DRV_SX1509_LEDDRIVERENABLE_PIN6_Disabled (0)
1799 #define DRV_SX1509_LEDDRIVERENABLE_PIN6_Enabled (1)
1802 /* Field PIN5: Enables LED Driver for each [output-configured] IO. */
1803 #define DRV_SX1509_LEDDRIVERENABLE_PIN5_Pos (5)
1804 #define DRV_SX1509_LEDDRIVERENABLE_PIN5_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN5_Pos)
1805 #define DRV_SX1509_LEDDRIVERENABLE_PIN5_Disabled (0)
1806 #define DRV_SX1509_LEDDRIVERENABLE_PIN5_Enabled (1)
1809 /* Field PIN4: Enables LED Driver for each [output-configured] IO. */
1810 #define DRV_SX1509_LEDDRIVERENABLE_PIN4_Pos (4)
1811 #define DRV_SX1509_LEDDRIVERENABLE_PIN4_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN4_Pos)
1812 #define DRV_SX1509_LEDDRIVERENABLE_PIN4_Disabled (0)
1813 #define DRV_SX1509_LEDDRIVERENABLE_PIN4_Enabled (1)
1816 /* Field PIN3: Enables LED Driver for each [output-configured] IO. */
1817 #define DRV_SX1509_LEDDRIVERENABLE_PIN3_Pos (3)
1818 #define DRV_SX1509_LEDDRIVERENABLE_PIN3_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN3_Pos)
1819 #define DRV_SX1509_LEDDRIVERENABLE_PIN3_Disabled (0)
1820 #define DRV_SX1509_LEDDRIVERENABLE_PIN3_Enabled (1)
1823 /* Field PIN2: Enables LED Driver for each [output-configured] IO. */
1824 #define DRV_SX1509_LEDDRIVERENABLE_PIN2_Pos (2)
1825 #define DRV_SX1509_LEDDRIVERENABLE_PIN2_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN2_Pos)
1826 #define DRV_SX1509_LEDDRIVERENABLE_PIN2_Disabled (0)
1827 #define DRV_SX1509_LEDDRIVERENABLE_PIN2_Enabled (1)
1830 /* Field PIN1: Enables LED Driver for each [output-configured] IO. */
1831 #define DRV_SX1509_LEDDRIVERENABLE_PIN1_Pos (1)
1832 #define DRV_SX1509_LEDDRIVERENABLE_PIN1_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN1_Pos)
1833 #define DRV_SX1509_LEDDRIVERENABLE_PIN1_Disabled (0)
1834 #define DRV_SX1509_LEDDRIVERENABLE_PIN1_Enabled (1)
1837 /* Field PIN0: Enables LED Driver for each [output-configured] IO. */
1838 #define DRV_SX1509_LEDDRIVERENABLE_PIN0_Pos (0)
1839 #define DRV_SX1509_LEDDRIVERENABLE_PIN0_Msk (0x1 << DRV_SX1509_LEDDRIVERENABLE_PIN0_Pos)
1840 #define DRV_SX1509_LEDDRIVERENABLE_PIN0_Disabled (0)
1841 #define DRV_SX1509_LEDDRIVERENABLE_PIN0_Enabled (1)
1844 /* Register: DEBOUNCECONFIG. */
1845 /* Description: Debounce configuration register. */
1846
1847
1848 /* Field RESERVED0: Unused field. */
1849 #define DRV_SX1509_DEBOUNCECONFIG_RESERVED0_Pos (3)
1850 #define DRV_SX1509_DEBOUNCECONFIG_RESERVED0_Msk (0x1F << DRV_SX1509_DEBOUNCECONFIG_RESERVED0_Pos)
1853 /* Field TIME: Debounce time (Cf. �4.6.1). */
1854 #define DRV_SX1509_DEBOUNCECONFIG_TIME_Pos (0)
1855 #define DRV_SX1509_DEBOUNCECONFIG_TIME_Msk (0x7 << DRV_SX1509_DEBOUNCECONFIG_TIME_Pos)
1856 #define DRV_SX1509_DEBOUNCECONFIG_TIME_0ms5 (0)
1857 #define DRV_SX1509_DEBOUNCECONFIG_TIME_1ms (1)
1858 #define DRV_SX1509_DEBOUNCECONFIG_TIME_2ms (2)
1859 #define DRV_SX1509_DEBOUNCECONFIG_TIME_4ms (3)
1860 #define DRV_SX1509_DEBOUNCECONFIG_TIME_8ms (4)
1861 #define DRV_SX1509_DEBOUNCECONFIG_TIME_16ms (5)
1862 #define DRV_SX1509_DEBOUNCECONFIG_TIME_32ms (6)
1863 #define DRV_SX1509_DEBOUNCECONFIG_TIME_64ms (7)
1866 /* Register: DEBOUNCEENABLE. */
1867 /* Description: Debounce enable register - I/O[n]. */
1868
1869
1870 /* Field PIN15: Enables debouncing for each [input-configured] IO. */
1871 #define DRV_SX1509_DEBOUNCEENABLE_PIN15_Pos (15)
1872 #define DRV_SX1509_DEBOUNCEENABLE_PIN15_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN15_Pos)
1873 #define DRV_SX1509_DEBOUNCEENABLE_PIN15_Disabled (0)
1874 #define DRV_SX1509_DEBOUNCEENABLE_PIN15_Enabled (1)
1877 /* Field PIN14: Enables debouncing for each [input-configured] IO. */
1878 #define DRV_SX1509_DEBOUNCEENABLE_PIN14_Pos (14)
1879 #define DRV_SX1509_DEBOUNCEENABLE_PIN14_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN14_Pos)
1880 #define DRV_SX1509_DEBOUNCEENABLE_PIN14_Disabled (0)
1881 #define DRV_SX1509_DEBOUNCEENABLE_PIN14_Enabled (1)
1884 /* Field PIN13: Enables debouncing for each [input-configured] IO. */
1885 #define DRV_SX1509_DEBOUNCEENABLE_PIN13_Pos (13)
1886 #define DRV_SX1509_DEBOUNCEENABLE_PIN13_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN13_Pos)
1887 #define DRV_SX1509_DEBOUNCEENABLE_PIN13_Disabled (0)
1888 #define DRV_SX1509_DEBOUNCEENABLE_PIN13_Enabled (1)
1891 /* Field PIN12: Enables debouncing for each [input-configured] IO. */
1892 #define DRV_SX1509_DEBOUNCEENABLE_PIN12_Pos (12)
1893 #define DRV_SX1509_DEBOUNCEENABLE_PIN12_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN12_Pos)
1894 #define DRV_SX1509_DEBOUNCEENABLE_PIN12_Disabled (0)
1895 #define DRV_SX1509_DEBOUNCEENABLE_PIN12_Enabled (1)
1898 /* Field PIN11: Enables debouncing for each [input-configured] IO. */
1899 #define DRV_SX1509_DEBOUNCEENABLE_PIN11_Pos (11)
1900 #define DRV_SX1509_DEBOUNCEENABLE_PIN11_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN11_Pos)
1901 #define DRV_SX1509_DEBOUNCEENABLE_PIN11_Disabled (0)
1902 #define DRV_SX1509_DEBOUNCEENABLE_PIN11_Enabled (1)
1905 /* Field PIN10: Enables debouncing for each [input-configured] IO. */
1906 #define DRV_SX1509_DEBOUNCEENABLE_PIN10_Pos (10)
1907 #define DRV_SX1509_DEBOUNCEENABLE_PIN10_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN10_Pos)
1908 #define DRV_SX1509_DEBOUNCEENABLE_PIN10_Disabled (0)
1909 #define DRV_SX1509_DEBOUNCEENABLE_PIN10_Enabled (1)
1912 /* Field PIN9: Enables debouncing for each [input-configured] IO. */
1913 #define DRV_SX1509_DEBOUNCEENABLE_PIN9_Pos (9)
1914 #define DRV_SX1509_DEBOUNCEENABLE_PIN9_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN9_Pos)
1915 #define DRV_SX1509_DEBOUNCEENABLE_PIN9_Disabled (0)
1916 #define DRV_SX1509_DEBOUNCEENABLE_PIN9_Enabled (1)
1919 /* Field PIN8: Enables debouncing for each [input-configured] IO. */
1920 #define DRV_SX1509_DEBOUNCEENABLE_PIN8_Pos (8)
1921 #define DRV_SX1509_DEBOUNCEENABLE_PIN8_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN8_Pos)
1922 #define DRV_SX1509_DEBOUNCEENABLE_PIN8_Disabled (0)
1923 #define DRV_SX1509_DEBOUNCEENABLE_PIN8_Enabled (1)
1926 /* Field PIN7: Enables debouncing for each [input-configured] IO. */
1927 #define DRV_SX1509_DEBOUNCEENABLE_PIN7_Pos (7)
1928 #define DRV_SX1509_DEBOUNCEENABLE_PIN7_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN7_Pos)
1929 #define DRV_SX1509_DEBOUNCEENABLE_PIN7_Disabled (0)
1930 #define DRV_SX1509_DEBOUNCEENABLE_PIN7_Enabled (1)
1933 /* Field PIN6: Enables debouncing for each [input-configured] IO. */
1934 #define DRV_SX1509_DEBOUNCEENABLE_PIN6_Pos (6)
1935 #define DRV_SX1509_DEBOUNCEENABLE_PIN6_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN6_Pos)
1936 #define DRV_SX1509_DEBOUNCEENABLE_PIN6_Disabled (0)
1937 #define DRV_SX1509_DEBOUNCEENABLE_PIN6_Enabled (1)
1940 /* Field PIN5: Enables debouncing for each [input-configured] IO. */
1941 #define DRV_SX1509_DEBOUNCEENABLE_PIN5_Pos (5)
1942 #define DRV_SX1509_DEBOUNCEENABLE_PIN5_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN5_Pos)
1943 #define DRV_SX1509_DEBOUNCEENABLE_PIN5_Disabled (0)
1944 #define DRV_SX1509_DEBOUNCEENABLE_PIN5_Enabled (1)
1947 /* Field PIN4: Enables debouncing for each [input-configured] IO. */
1948 #define DRV_SX1509_DEBOUNCEENABLE_PIN4_Pos (4)
1949 #define DRV_SX1509_DEBOUNCEENABLE_PIN4_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN4_Pos)
1950 #define DRV_SX1509_DEBOUNCEENABLE_PIN4_Disabled (0)
1951 #define DRV_SX1509_DEBOUNCEENABLE_PIN4_Enabled (1)
1954 /* Field PIN3: Enables debouncing for each [input-configured] IO. */
1955 #define DRV_SX1509_DEBOUNCEENABLE_PIN3_Pos (3)
1956 #define DRV_SX1509_DEBOUNCEENABLE_PIN3_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN3_Pos)
1957 #define DRV_SX1509_DEBOUNCEENABLE_PIN3_Disabled (0)
1958 #define DRV_SX1509_DEBOUNCEENABLE_PIN3_Enabled (1)
1961 /* Field PIN2: Enables debouncing for each [input-configured] IO. */
1962 #define DRV_SX1509_DEBOUNCEENABLE_PIN2_Pos (2)
1963 #define DRV_SX1509_DEBOUNCEENABLE_PIN2_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN2_Pos)
1964 #define DRV_SX1509_DEBOUNCEENABLE_PIN2_Disabled (0)
1965 #define DRV_SX1509_DEBOUNCEENABLE_PIN2_Enabled (1)
1968 /* Field PIN1: Enables debouncing for each [input-configured] IO. */
1969 #define DRV_SX1509_DEBOUNCEENABLE_PIN1_Pos (1)
1970 #define DRV_SX1509_DEBOUNCEENABLE_PIN1_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN1_Pos)
1971 #define DRV_SX1509_DEBOUNCEENABLE_PIN1_Disabled (0)
1972 #define DRV_SX1509_DEBOUNCEENABLE_PIN1_Enabled (1)
1975 /* Field PIN0: Enables debouncing for each [input-configured] IO. */
1976 #define DRV_SX1509_DEBOUNCEENABLE_PIN0_Pos (0)
1977 #define DRV_SX1509_DEBOUNCEENABLE_PIN0_Msk (0x1 << DRV_SX1509_DEBOUNCEENABLE_PIN0_Pos)
1978 #define DRV_SX1509_DEBOUNCEENABLE_PIN0_Disabled (0)
1979 #define DRV_SX1509_DEBOUNCEENABLE_PIN0_Enabled (1)
1982 /* Register: KEYCONFIG. */
1983 /* Description: Key scan configuration register. */
1984
1985
1986 /* Field RESERVED2: Unused field. */
1987 #define DRV_SX1509_KEYCONFIG_RESERVED2_Pos (15)
1988 #define DRV_SX1509_KEYCONFIG_RESERVED2_Msk (0x1 << DRV_SX1509_KEYCONFIG_RESERVED2_Pos)
1991 /* Field AUTOSLEEPTIME: Auto Sleep time (no key press within this time will set keypad engine to sleep). */
1992 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_Pos (12)
1993 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_Msk (0x7 << DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_Pos)
1994 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_Off (0)
1995 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_128ms (1)
1996 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_256ms (2)
1997 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_512ms (3)
1998 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_1s (4)
1999 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_2s (5)
2000 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_4s (6)
2001 #define DRV_SX1509_KEYCONFIG_AUTOSLEEPTIME_8s (7)
2004 /* Field RESERVED1: Unused field. */
2005 #define DRV_SX1509_KEYCONFIG_RESERVED1_Pos (11)
2006 #define DRV_SX1509_KEYCONFIG_RESERVED1_Msk (0x1 << DRV_SX1509_KEYCONFIG_RESERVED1_Pos)
2009 /* Field SCANTIME: Scan time per row (must be set above debounce time). */
2010 #define DRV_SX1509_KEYCONFIG_SCANTIME_Pos (8)
2011 #define DRV_SX1509_KEYCONFIG_SCANTIME_Msk (0x7 << DRV_SX1509_KEYCONFIG_SCANTIME_Pos)
2012 #define DRV_SX1509_KEYCONFIG_SCANTIME_1ms (0)
2013 #define DRV_SX1509_KEYCONFIG_SCANTIME_2ms (1)
2014 #define DRV_SX1509_KEYCONFIG_SCANTIME_4ms (2)
2015 #define DRV_SX1509_KEYCONFIG_SCANTIME_8ms (3)
2016 #define DRV_SX1509_KEYCONFIG_SCANTIME_16ms (4)
2017 #define DRV_SX1509_KEYCONFIG_SCANTIME_32ms (5)
2018 #define DRV_SX1509_KEYCONFIG_SCANTIME_64ms (6)
2019 #define DRV_SX1509_KEYCONFIG_SCANTIME_128ms (7)
2022 /* Field RESERVED0: Unused field. */
2023 #define DRV_SX1509_KEYCONFIG_RESERVED0_Pos (6)
2024 #define DRV_SX1509_KEYCONFIG_RESERVED0_Msk (0x3 << DRV_SX1509_KEYCONFIG_RESERVED0_Pos)
2027 /* Field ROWS: Number of rows (outputs) + key scan enable. */
2028 #define DRV_SX1509_KEYCONFIG_ROWS_Pos (3)
2029 #define DRV_SX1509_KEYCONFIG_ROWS_Msk (0x7 << DRV_SX1509_KEYCONFIG_ROWS_Pos)
2030 #define DRV_SX1509_KEYCONFIG_ROWS_Off (0)
2031 #define DRV_SX1509_KEYCONFIG_ROWS_2Rows (1)
2032 #define DRV_SX1509_KEYCONFIG_ROWS_3Rows (2)
2033 #define DRV_SX1509_KEYCONFIG_ROWS_4Rows (3)
2034 #define DRV_SX1509_KEYCONFIG_ROWS_5Rows (4)
2035 #define DRV_SX1509_KEYCONFIG_ROWS_6Rows (5)
2036 #define DRV_SX1509_KEYCONFIG_ROWS_7Rows (6)
2037 #define DRV_SX1509_KEYCONFIG_ROWS_8Rows (7)
2040 /* Field COLS: Number of columns (inputs). */
2041 #define DRV_SX1509_KEYCONFIG_COLS_Pos (0)
2042 #define DRV_SX1509_KEYCONFIG_COLS_Msk (0x7 << DRV_SX1509_KEYCONFIG_COLS_Pos)
2043 #define DRV_SX1509_KEYCONFIG_COLS_1Col (0)
2044 #define DRV_SX1509_KEYCONFIG_COLS_2Cols (1)
2045 #define DRV_SX1509_KEYCONFIG_COLS_3Cols (2)
2046 #define DRV_SX1509_KEYCONFIG_COLS_4Cols (3)
2047 #define DRV_SX1509_KEYCONFIG_COLS_5Cols (4)
2048 #define DRV_SX1509_KEYCONFIG_COLS_6Cols (5)
2049 #define DRV_SX1509_KEYCONFIG_COLS_7Cols (6)
2050 #define DRV_SX1509_KEYCONFIG_COLS_8Cols (7)
2053 /* Register: KEYDATA. */
2054 /* Description: Key value. */
2055
2056
2057 /* Field COLINTR7: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2058 #define DRV_SX1509_KEYDATA_COLINTR7_Pos (15)
2059 #define DRV_SX1509_KEYDATA_COLINTR7_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR7_Pos)
2060 #define DRV_SX1509_KEYDATA_COLINTR7_None (0)
2061 #define DRV_SX1509_KEYDATA_COLINTR7_Triggered (1)
2064 /* Field COLINTR6: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2065 #define DRV_SX1509_KEYDATA_COLINTR6_Pos (14)
2066 #define DRV_SX1509_KEYDATA_COLINTR6_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR6_Pos)
2067 #define DRV_SX1509_KEYDATA_COLINTR6_None (0)
2068 #define DRV_SX1509_KEYDATA_COLINTR6_Triggered (1)
2071 /* Field COLINTR5: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2072 #define DRV_SX1509_KEYDATA_COLINTR5_Pos (13)
2073 #define DRV_SX1509_KEYDATA_COLINTR5_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR5_Pos)
2074 #define DRV_SX1509_KEYDATA_COLINTR5_None (0)
2075 #define DRV_SX1509_KEYDATA_COLINTR5_Triggered (1)
2078 /* Field COLINTR4: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2079 #define DRV_SX1509_KEYDATA_COLINTR4_Pos (12)
2080 #define DRV_SX1509_KEYDATA_COLINTR4_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR4_Pos)
2081 #define DRV_SX1509_KEYDATA_COLINTR4_None (0)
2082 #define DRV_SX1509_KEYDATA_COLINTR4_Triggered (1)
2085 /* Field COLINTR3: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2086 #define DRV_SX1509_KEYDATA_COLINTR3_Pos (11)
2087 #define DRV_SX1509_KEYDATA_COLINTR3_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR3_Pos)
2088 #define DRV_SX1509_KEYDATA_COLINTR3_None (0)
2089 #define DRV_SX1509_KEYDATA_COLINTR3_Triggered (1)
2092 /* Field COLINTR2: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2093 #define DRV_SX1509_KEYDATA_COLINTR2_Pos (10)
2094 #define DRV_SX1509_KEYDATA_COLINTR2_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR2_Pos)
2095 #define DRV_SX1509_KEYDATA_COLINTR2_None (0)
2096 #define DRV_SX1509_KEYDATA_COLINTR2_Triggered (1)
2099 /* Field COLINTR1: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2100 #define DRV_SX1509_KEYDATA_COLINTR1_Pos (9)
2101 #define DRV_SX1509_KEYDATA_COLINTR1_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR1_Pos)
2102 #define DRV_SX1509_KEYDATA_COLINTR1_None (0)
2103 #define DRV_SX1509_KEYDATA_COLINTR1_Triggered (1)
2106 /* Field COLINTR0: Column which generated NINT (active low in HW, intentionally active high through driver interface). */
2107 #define DRV_SX1509_KEYDATA_COLINTR0_Pos (8)
2108 #define DRV_SX1509_KEYDATA_COLINTR0_Msk (0x1 << DRV_SX1509_KEYDATA_COLINTR0_Pos)
2109 #define DRV_SX1509_KEYDATA_COLINTR0_None (0)
2110 #define DRV_SX1509_KEYDATA_COLINTR0_Triggered (1)
2113 /* Field ROWINTR7: Row which generated NINT (active low). */
2114 #define DRV_SX1509_KEYDATA_ROWINTR7_Pos (7)
2115 #define DRV_SX1509_KEYDATA_ROWINTR7_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR7_Pos)
2116 #define DRV_SX1509_KEYDATA_ROWINTR7_None (0)
2117 #define DRV_SX1509_KEYDATA_ROWINTR7_Triggered (1)
2120 /* Field ROWINTR6: Row which generated NINT (active low). */
2121 #define DRV_SX1509_KEYDATA_ROWINTR6_Pos (6)
2122 #define DRV_SX1509_KEYDATA_ROWINTR6_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR6_Pos)
2123 #define DRV_SX1509_KEYDATA_ROWINTR6_None (0)
2124 #define DRV_SX1509_KEYDATA_ROWINTR6_Triggered (1)
2127 /* Field ROWINTR5: Row which generated NINT (active low). */
2128 #define DRV_SX1509_KEYDATA_ROWINTR5_Pos (5)
2129 #define DRV_SX1509_KEYDATA_ROWINTR5_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR5_Pos)
2130 #define DRV_SX1509_KEYDATA_ROWINTR5_None (0)
2131 #define DRV_SX1509_KEYDATA_ROWINTR5_Triggered (1)
2134 /* Field ROWINTR4: Row which generated NINT (active low). */
2135 #define DRV_SX1509_KEYDATA_ROWINTR4_Pos (4)
2136 #define DRV_SX1509_KEYDATA_ROWINTR4_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR4_Pos)
2137 #define DRV_SX1509_KEYDATA_ROWINTR4_None (0)
2138 #define DRV_SX1509_KEYDATA_ROWINTR4_Triggered (1)
2141 /* Field ROWINTR3: Row which generated NINT (active low). */
2142 #define DRV_SX1509_KEYDATA_ROWINTR3_Pos (3)
2143 #define DRV_SX1509_KEYDATA_ROWINTR3_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR3_Pos)
2144 #define DRV_SX1509_KEYDATA_ROWINTR3_None (0)
2145 #define DRV_SX1509_KEYDATA_ROWINTR3_Triggered (1)
2148 /* Field ROWINTR2: Row which generated NINT (active low). */
2149 #define DRV_SX1509_KEYDATA_ROWINTR2_Pos (2)
2150 #define DRV_SX1509_KEYDATA_ROWINTR2_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR2_Pos)
2151 #define DRV_SX1509_KEYDATA_ROWINTR2_None (0)
2152 #define DRV_SX1509_KEYDATA_ROWINTR2_Triggered (1)
2155 /* Field ROWINTR1: Row which generated NINT (active low). */
2156 #define DRV_SX1509_KEYDATA_ROWINTR1_Pos (1)
2157 #define DRV_SX1509_KEYDATA_ROWINTR1_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR1_Pos)
2158 #define DRV_SX1509_KEYDATA_ROWINTR1_None (0)
2159 #define DRV_SX1509_KEYDATA_ROWINTR1_Triggered (1)
2162 /* Field ROWINTR0: Row which generated NINT (active low). */
2163 #define DRV_SX1509_KEYDATA_ROWINTR0_Pos (0)
2164 #define DRV_SX1509_KEYDATA_ROWINTR0_Msk (0x1 << DRV_SX1509_KEYDATA_ROWINTR0_Pos)
2165 #define DRV_SX1509_KEYDATA_ROWINTR0_None (0)
2166 #define DRV_SX1509_KEYDATA_ROWINTR0_Triggered (1)
2169 /* Register: ONOFFCFGX. */
2170 /* Description: ON/OFF time/intensity register for I/O[n]. */
2171
2172
2173 /* Field RESERVED0: Unused field. */
2174 #define DRV_SX1509_ONOFFCFGX_RESERVED0_Pos (21)
2175 #define DRV_SX1509_ONOFFCFGX_RESERVED0_Msk (0x7 << DRV_SX1509_ONOFFCFGX_RESERVED0_Pos)
2178 /* Field ONTIME: ON Time of IO[n] (1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX), 16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX)). */
2179 #define DRV_SX1509_ONOFFCFGX_ONTIME_Pos (16)
2180 #define DRV_SX1509_ONOFFCFGX_ONTIME_Msk (0x1F << DRV_SX1509_ONOFFCFGX_ONTIME_Pos)
2181 #define DRV_SX1509_ONOFFCFGX_ONTIME_Infinite (0)
2184 /* Field ONINTENSITY: ON Intensity of IO[n] (Linear mode : IOnX = RegIOnN, Logarithmic mode (fading capable IOs only, Cf �4.9.5) : IOnN = f(RegIOnN)). */
2185 #define DRV_SX1509_ONOFFCFGX_ONINTENSITY_Pos (8)
2186 #define DRV_SX1509_ONOFFCFGX_ONINTENSITY_Msk (0xFF << DRV_SX1509_ONOFFCFGX_ONINTENSITY_Pos)
2189 /* Field OFFTIME: OFF Time of IO[n], (1 - 15 : TOffN = 64 * RegOffN[7:3] * (255/ClkN), 16 - 31 : TOffN = 512 * RegOffN[7:3] * (255/ClkN)). */
2190 #define DRV_SX1509_ONOFFCFGX_OFFTIME_Pos (3)
2191 #define DRV_SX1509_ONOFFCFGX_OFFTIME_Msk (0x1F << DRV_SX1509_ONOFFCFGX_OFFTIME_Pos)
2192 #define DRV_SX1509_ONOFFCFGX_OFFTIME_Infinite (0)
2195 /* Field OFFINTENSITY: OFF Intensity of IO[n] (Linear mode : IOffN = 4 x RegOff[2:0], Logarithmic mode (fading capable IOs only, Cf �4.9.5) : IOffN = f(4 x RegOffN[2:0])). */
2196 #define DRV_SX1509_ONOFFCFGX_OFFINTENSITY_Pos (0)
2197 #define DRV_SX1509_ONOFFCFGX_OFFINTENSITY_Msk (0x7 << DRV_SX1509_ONOFFCFGX_OFFINTENSITY_Pos)
2200 /* Register: RISEFALLCFGX. */
2201 /* Description: Fade configuration register for I/O[n]. */
2202
2203
2204 /* Field RESERVED1: Unused field. */
2205 #define DRV_SX1509_RISEFALLCFGX_RESERVED1_Pos (13)
2206 #define DRV_SX1509_RISEFALLCFGX_RESERVED1_Msk (0x7 << DRV_SX1509_RISEFALLCFGX_RESERVED1_Pos)
2209 /* Field FADEIN: Fade In setting of IO[n], (1 - 15 : TRiseN = (RegIOnN-(4x<OffIntensity>)) * <FadeIn> * (255/ClkN) 16 - 31 : TRiseN = 16 * (<OnTime>-(4x<OffIntensity>)) * <FadeIn> * (255/ClkN)). */
2210 #define DRV_SX1509_RISEFALLCFGX_FADEIN_Pos (8)
2211 #define DRV_SX1509_RISEFALLCFGX_FADEIN_Msk (0x1F << DRV_SX1509_RISEFALLCFGX_FADEIN_Pos)
2212 #define DRV_SX1509_RISEFALLCFGX_FADEIN_Off (0)
2215 /* Field RESERVED0: Unused field. */
2216 #define DRV_SX1509_RISEFALLCFGX_RESERVED0_Pos (5)
2217 #define DRV_SX1509_RISEFALLCFGX_RESERVED0_Msk (0x7 << DRV_SX1509_RISEFALLCFGX_RESERVED0_Pos)
2220 /* Field FADEOUT: Fade Out setting of IO[n], (1 - 15 : TFallN = (RegIOnN-(4x<OffIntensity>)) * <FadeOut> * (255/ClkN) 16 - 31 : TFallN = 16 * (<OnTime>-(4x<OffIntensity>)) * <FadeOut> * (255/ClkN)). */
2221 #define DRV_SX1509_RISEFALLCFGX_FADEOUT_Pos (0)
2222 #define DRV_SX1509_RISEFALLCFGX_FADEOUT_Msk (0x1F << DRV_SX1509_RISEFALLCFGX_FADEOUT_Pos)
2223 #define DRV_SX1509_RISEFALLCFGX_FADEOUT_Off (0)
2226 /* Register: HIGHINPMODE. */
2227 /* Description: High input enable register. */
2228
2229
2230 /* Field PIN15: Enables high input mode for each (input-configured) IO. */
2231 #define DRV_SX1509_HIGHINPMODE_PIN15_Pos (15)
2232 #define DRV_SX1509_HIGHINPMODE_PIN15_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN15_Pos)
2233 #define DRV_SX1509_HIGHINPMODE_PIN15_Disabled (0)
2234 #define DRV_SX1509_HIGHINPMODE_PIN15_Enabled (1)
2237 /* Field PIN14: Enables high input mode for each (input-configured) IO. */
2238 #define DRV_SX1509_HIGHINPMODE_PIN14_Pos (14)
2239 #define DRV_SX1509_HIGHINPMODE_PIN14_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN14_Pos)
2240 #define DRV_SX1509_HIGHINPMODE_PIN14_Disabled (0)
2241 #define DRV_SX1509_HIGHINPMODE_PIN14_Enabled (1)
2244 /* Field PIN13: Enables high input mode for each (input-configured) IO. */
2245 #define DRV_SX1509_HIGHINPMODE_PIN13_Pos (13)
2246 #define DRV_SX1509_HIGHINPMODE_PIN13_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN13_Pos)
2247 #define DRV_SX1509_HIGHINPMODE_PIN13_Disabled (0)
2248 #define DRV_SX1509_HIGHINPMODE_PIN13_Enabled (1)
2251 /* Field PIN12: Enables high input mode for each (input-configured) IO. */
2252 #define DRV_SX1509_HIGHINPMODE_PIN12_Pos (12)
2253 #define DRV_SX1509_HIGHINPMODE_PIN12_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN12_Pos)
2254 #define DRV_SX1509_HIGHINPMODE_PIN12_Disabled (0)
2255 #define DRV_SX1509_HIGHINPMODE_PIN12_Enabled (1)
2258 /* Field PIN11: Enables high input mode for each (input-configured) IO. */
2259 #define DRV_SX1509_HIGHINPMODE_PIN11_Pos (11)
2260 #define DRV_SX1509_HIGHINPMODE_PIN11_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN11_Pos)
2261 #define DRV_SX1509_HIGHINPMODE_PIN11_Disabled (0)
2262 #define DRV_SX1509_HIGHINPMODE_PIN11_Enabled (1)
2265 /* Field PIN10: Enables high input mode for each (input-configured) IO. */
2266 #define DRV_SX1509_HIGHINPMODE_PIN10_Pos (10)
2267 #define DRV_SX1509_HIGHINPMODE_PIN10_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN10_Pos)
2268 #define DRV_SX1509_HIGHINPMODE_PIN10_Disabled (0)
2269 #define DRV_SX1509_HIGHINPMODE_PIN10_Enabled (1)
2272 /* Field PIN9: Enables high input mode for each (input-configured) IO. */
2273 #define DRV_SX1509_HIGHINPMODE_PIN9_Pos (9)
2274 #define DRV_SX1509_HIGHINPMODE_PIN9_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN9_Pos)
2275 #define DRV_SX1509_HIGHINPMODE_PIN9_Disabled (0)
2276 #define DRV_SX1509_HIGHINPMODE_PIN9_Enabled (1)
2279 /* Field PIN8: Enables high input mode for each (input-configured) IO. */
2280 #define DRV_SX1509_HIGHINPMODE_PIN8_Pos (8)
2281 #define DRV_SX1509_HIGHINPMODE_PIN8_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN8_Pos)
2282 #define DRV_SX1509_HIGHINPMODE_PIN8_Disabled (0)
2283 #define DRV_SX1509_HIGHINPMODE_PIN8_Enabled (1)
2286 /* Field PIN7: Enables high input mode for each (input-configured) IO. */
2287 #define DRV_SX1509_HIGHINPMODE_PIN7_Pos (7)
2288 #define DRV_SX1509_HIGHINPMODE_PIN7_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN7_Pos)
2289 #define DRV_SX1509_HIGHINPMODE_PIN7_Disabled (0)
2290 #define DRV_SX1509_HIGHINPMODE_PIN7_Enabled (1)
2293 /* Field PIN6: Enables high input mode for each (input-configured) IO. */
2294 #define DRV_SX1509_HIGHINPMODE_PIN6_Pos (6)
2295 #define DRV_SX1509_HIGHINPMODE_PIN6_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN6_Pos)
2296 #define DRV_SX1509_HIGHINPMODE_PIN6_Disabled (0)
2297 #define DRV_SX1509_HIGHINPMODE_PIN6_Enabled (1)
2300 /* Field PIN5: Enables high input mode for each (input-configured) IO. */
2301 #define DRV_SX1509_HIGHINPMODE_PIN5_Pos (5)
2302 #define DRV_SX1509_HIGHINPMODE_PIN5_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN5_Pos)
2303 #define DRV_SX1509_HIGHINPMODE_PIN5_Disabled (0)
2304 #define DRV_SX1509_HIGHINPMODE_PIN5_Enabled (1)
2307 /* Field PIN4: Enables high input mode for each (input-configured) IO. */
2308 #define DRV_SX1509_HIGHINPMODE_PIN4_Pos (4)
2309 #define DRV_SX1509_HIGHINPMODE_PIN4_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN4_Pos)
2310 #define DRV_SX1509_HIGHINPMODE_PIN4_Disabled (0)
2311 #define DRV_SX1509_HIGHINPMODE_PIN4_Enabled (1)
2314 /* Field PIN3: Enables high input mode for each (input-configured) IO. */
2315 #define DRV_SX1509_HIGHINPMODE_PIN3_Pos (3)
2316 #define DRV_SX1509_HIGHINPMODE_PIN3_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN3_Pos)
2317 #define DRV_SX1509_HIGHINPMODE_PIN3_Disabled (0)
2318 #define DRV_SX1509_HIGHINPMODE_PIN3_Enabled (1)
2321 /* Field PIN2: Enables high input mode for each (input-configured) IO. */
2322 #define DRV_SX1509_HIGHINPMODE_PIN2_Pos (2)
2323 #define DRV_SX1509_HIGHINPMODE_PIN2_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN2_Pos)
2324 #define DRV_SX1509_HIGHINPMODE_PIN2_Disabled (0)
2325 #define DRV_SX1509_HIGHINPMODE_PIN2_Enabled (1)
2328 /* Field PIN1: Enables high input mode for each (input-configured) IO. */
2329 #define DRV_SX1509_HIGHINPMODE_PIN1_Pos (1)
2330 #define DRV_SX1509_HIGHINPMODE_PIN1_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN1_Pos)
2331 #define DRV_SX1509_HIGHINPMODE_PIN1_Disabled (0)
2332 #define DRV_SX1509_HIGHINPMODE_PIN1_Enabled (1)
2335 /* Field PIN0: Enables high input mode for each (input-configured) IO. */
2336 #define DRV_SX1509_HIGHINPMODE_PIN0_Pos (0)
2337 #define DRV_SX1509_HIGHINPMODE_PIN0_Msk (0x1 << DRV_SX1509_HIGHINPMODE_PIN0_Pos)
2338 #define DRV_SX1509_HIGHINPMODE_PIN0_Disabled (0)
2339 #define DRV_SX1509_HIGHINPMODE_PIN0_Enabled (1)
2342 /* Register: RESET. */
2343 /* Description: Software reset register. */
2344
2345
2346 /* Field CODE: Reset code. */
2347 #define DRV_SX1509_RESET_CODE_Pos (0)
2348 #define DRV_SX1509_RESET_CODE_Msk (0xFFFF << DRV_SX1509_RESET_CODE_Pos)
2349 #define DRV_SX1509_RESET_CODE_Reset (0x1234)
2351 #endif // DRV_SX1509_BITFIELDS_H__