| Nordic Thingy:52 v2.0.0

drv_acc_lis3dh_types.h
1 /*
2 Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
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8 1. Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
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11 2. Redistributions in binary form, except as embedded into a Nordic
12 Semiconductor ASA integrated circuit in a product or a software update for
13 such product, must reproduce the above copyright notice, this list of
14 conditions and the following disclaimer in the documentation and/or other
15 materials provided with the distribution.
16
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18 contributors may be used to endorse or promote products derived from this
19 software without specific prior written permission.
20
21 4. This software, with or without modification, must only be used with a
22 Nordic Semiconductor ASA integrated circuit.
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24 5. Any software provided in binary form under this license must not be reverse
25 engineered, decompiled, modified and/or disassembled.
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37 */
38
47 #ifndef __DRV_ACC_LIS3DH_TYPES_H__
48 #define __DRV_ACC_LIS3DH_TYPES_H__
49
50 #include <stdint.h>
51
54 typedef enum
55 {
56 ODR_1Hz = 0x01,
57 ODR_10Hz = 0x02,
58 ODR_25Hz = 0x03,
59 ODR_50Hz = 0x04,
60 ODR_100Hz = 0x05,
61 ODR_200Hz = 0x06,
62 ODR_400Hz = 0x07,
63 ODR_1620Hz_LP = 0x08,
64 ODR_1344Hz_NP_5367HZ_LP = 0x09
65 } ODR_t;
66
69 typedef enum
70 {
71 POWER_DOWN = 0x00,
72 LOW_POWER = 0x01,
73 NORMAL = 0x02
74 } Mode_t;
75
78 typedef enum
79 {
80 FULLSCALE_2 = 0x00,
81 FULLSCALE_4 = 0x01,
82 FULLSCALE_8 = 0x02,
83 FULLSCALE_16 = 0x03
84 } Fullscale_t;
85
88 typedef enum
89 {
90 X_ENABLE = 0x01,
91 Y_ENABLE = 0x02,
92 Z_ENABLE = 0x04,
93 } AXISenable_t;
94
97 typedef enum
98 {
99 IntOR = 0x00,
100 Int6DMov = 0x01,
101 IntAND = 0x02,
102 Int6DPos = 0x03,
103 Int4DMov = 0x05,
104 Int4DPos = 0x07,
105 } IntMode_t;
106
109 typedef enum
110 {
111 IntActiveHigh = 0x00,
112 IntActiveLow = 0x02
113 } IntPolarity_t;
114
117 typedef enum
118 {
119 ClickSingle = 0x00,
120 ClickDouble = 0x01,
121 } ClickMode_t;
122
125 typedef enum
126 {
127 HPNormalRes = 0x00,
128 HPReference = 0x01,
129 HPNormal = 0x02,
130 HPAutoResInt = 0x03
131 } HPFilterMode_t;
132
135 typedef struct
136 {
137 int16_t AXIS_X;
138 int16_t AXIS_Y;
139 int16_t AXIS_Z;
140 } AccAxesRaw_t;
141
142 // Aux status register.
143 #define STATUS_AUX 0x07
144 #define STATUS_AUX_TOR BIT_6
145 #define STATUS_AUX_TDA BIT_2
146
147 // Temperature sensor data register.
148 #define OUT_TEMP_L 0x0C
149 #define OUT_TEMP_H 0x0D
150
151 // Device identification register.
152 #define WHO_AM_I 0x0F
153 #define I_AM_LIS3DH 0x33
154
155 // Control register 0.
156 #define CTRL_REG0 0x1E
157 #define CTRL_REG0_SDO_PU_DISC BIT_7
158 #define CTRL_REG0_CORRECT_OPER BIT_4
159
160 // Temperature configuration register.
161 #define TEMP_CFG_REG 0x1F
162 #define TEMP_CFG_REG_TEMP1_EN BIT_7
163 #define TEMP_CFG_REG_TEMP2_EN BIT_6
164
165 // Control register 1.
166 #define CTRL_REG1 0x20
167 #define CTRL_REG1_ODR_BITS_MASK 0xF0
168 #define CTRL_REG1_ODR_BIT BIT_4
169 #define CTRL_REG1_LPEN BIT_3
170 #define CTRL_REG1_ZEN BIT_2
171 #define CTRL_REG1_YEN BIT_1
172 #define CTRL_REG1_XEN BIT_0
173
174 // Control register 2
175 #define CTRL_REG2 0x21
176 #define CTRL_REG2_HPM BIT_6
177 #define CTRL_REG2_HPCF BIT_4
178 #define CTRL_REG2_FDS BIT_3
179 #define CTRL_REG2_HPCLICK BIT_2
180 #define CTRL_REG2_HP_IA2 BIT_1
181 #define CTRL_REG2_HP_IA1 BIT_0
182
183 // Control register 3
184 #define CTRL_REG3 0x22
185 #define CTRL_REG3_I1_CLICK BIT_7
186 #define CTRL_REG3_I1_IA1 BIT_6
187 #define CTRL_REG3_I1_IA2 BIT_5
188 #define CTRL_REG3_I1_ZYXDA BIT_4
189 #define CTRL_REG3_I1_WTM BIT_2
190 #define CTRL_REG3_I1_ORUN BIT_1
191
192 // Control register 4
193 #define CTRL_REG4 0x23
194 #define CTRL_REG4_BDU BIT_7
195 #define CTRL_REG4_BLE BIT_6
196 #define CTRL_REG4_FS1 BIT_5
197 #define CTRL_REG4_FS0 BIT_4
198 #define CTRL_REG4_HR BIT_3
199 #define CTRL_REG4_ST BIT_1
200 #define CTRL_REG4_SIM BIT_0
201
202 // Control register 5
203 #define CTRL_REG5 0x24
204 #define CTRL_REG5_BOOT BIT_7
205 #define CTRL_REG5_FIFO_EN BIT_6
206 #define CTRL_REG5_LIR_INT1 BIT_3
207 #define CTRL_REG5_D4D_INT1 BIT_2
208 #define CTRL_REG5_LIR_INT2 BIT_1
209 #define CTRL_REG5_D4D_INT2 BIT_0
210
211 // Control register 6
212 #define CTRL_REG6 0x25
213 #define CTRL_REG_6_I2_CLICK BIT_7
214 #define CTRL_REG_6_I2_IA1 BIT_6
215 #define CTRL_REG_6_I2_IA2 BIT_5
216 #define CTRL_REG_6_I2_BOOT BIT_4
217 #define CTRL_REG_6_I2_ACT BIT_3
218 #define CTRL_REG_6_INT_POLARITY BIT_1
219
220 // Reference/datacapture register.
221 #define REFERENCE_REG 0x26
222 #define REF0 BIT_0
223
224 // Axis status register.
225 #define STATUS_REG 0x27
226 #define ZYXOR BIT_7
227 #define ZOR BIT_6
228 #define YOR BIT_5
229 #define XOR BIT_4
230 #define ZYXDA BIT_3
231 #define ZDA BIT_2
232 #define YDA BIT_1
233 #define XDA BIT_0
234
235 // Acceleration data registers.
236 #define OUT_X_L 0x28
237 #define OUT_X_H 0x29
238 #define OUT_Y_L 0x2A
239 #define OUT_Y_H 0x2B
240 #define OUT_Z_L 0x2C
241 #define OUT_Z_H 0x2D
242
243 // FIFO registers.
244 #define FIFO_CTRL_REG 0x2E
245 #define FIFO_CTRL_REG_FM1 BIT_7
246 #define FIFO_CTRL_REG_FM0 BIT_6
247 #define FIFO_CTRL_REG_TR BIT_5
248 #define FIFO_CTRL_REG_FTH4 BIT_4
249 #define FIFO_CTRL_REG_FTH3 BIT_3
250 #define FIFO_CTRL_REG_FTH2 BIT_2
251 #define FIFO_CTRL_REG_FTH1 BIT_1
252 #define FIFO_CTRL_REG_FTH0 BIT_0
253
254 #define FIFO_SRC_REG 0x2F
255 #define FIFO_SRC_REG_WTM BIT_7
256 #define FIFO_SRC_REG_OVRN_INFO BIT_6
257 #define FIFO_SRC_REG_EMPTY BIT_5
258 #define FIFO_SRC_REG_FSS4 BIT_4
259 #define FIFO_SRC_REG_FSS3 BIT_3
260 #define FIFO_SRC_REG_FSS2 BIT_2
261 #define FIFO_SRC_REG_FSS1 BIT_1
262 #define FIFO_SRC_REG_FSS0 BIT_0
263
264 // Interrupt 1 registers.
265 #define INT1_CFG 0x30
266 #define INT1_CFG_ANDOR BIT_7
267 #define INT1_CFG_INT_6D BIT_6
268 #define INT1_CFG_ZHIE BIT_5
269 #define INT1_CFG_ZLIE BIT_4
270 #define INT1_CFG_YHIE BIT_3
271 #define INT1_CFG_YLIE BIT_2
272 #define INT1_CFG_XHIE BIT_1
273 #define INT1_CFG_XLIE BIT_0
274
275 #define INT1_SRC 0x31
276 #define INT1_SRC_IA BIT_6
277 #define INT1_SRC_ZH BIT_5
278 #define INT1_SRC_ZL BIT_4
279 #define INT1_SRC_YH BIT_3
280 #define INT1_SRC_YL BIT_2
281 #define INT1_SRC_XH BIT_1
282 #define INT1_SRC_XL BIT_0
283
284 #define INT1_THS 0x32
285 #define INT1_THS_THS6 BIT_6
286 #define INT1_THS_THS5 BIT_5
287 #define INT1_THS_THS4 BIT_4
288 #define INT1_THS_THS3 BIT_3
289 #define INT1_THS_THS2 BIT_2
290 #define INT1_THS_THS1 BIT_1
291 #define INT1_THS_THS0 BIT_0
292
293 #define INT1_DURATION 0x33
294 #define INT1_DURATION_D6 BIT_6
295 #define INT1_DURATION_D5 BIT_5
296 #define INT1_DURATION_D4 BIT_4
297 #define INT1_DURATION_D3 BIT_3
298 #define INT1_DURATION_D2 BIT_2
299 #define INT1_DURATION_D1 BIT_1
300 #define INT1_DURATION_D0 BIT_0
301
302 // Interrupt 2 registers.
303 #define INT2_CFG 0x34
304 #define INT2_CFG_ANDOR BIT_7
305 #define INT2_CFG_INT_6D BIT_6
306 #define INT2_CFG_ZHIE BIT_5
307 #define INT2_CFG_ZLIE BIT_4
308 #define INT2_CFG_YHIE BIT_3
309 #define INT2_CFG_YLIE BIT_2
310 #define INT2_CFG_XHIE BIT_1
311 #define INT2_CFG_XLIE BIT_0
312
313 #define INT2_SRC 0x35
314 #define INT2_SRC_IA BIT_6
315 #define INT2_SRC_ZH BIT_5
316 #define INT2_SRC_ZL BIT_4
317 #define INT2_SRC_YH BIT_3
318 #define INT2_SRC_YL BIT_2
319 #define INT2_SRC_XH BIT_1
320 #define INT2_SRC_XL BIT_0
321
322 #define INT2_THS 0x36
323 #define INT2_THS_THS6 BIT_6
324 #define INT2_THS_THS5 BIT_5
325 #define INT2_THS_THS4 BIT_4
326 #define INT2_THS_THS3 BIT_3
327 #define INT2_THS_THS2 BIT_2
328 #define INT2_THS_THS1 BIT_1
329 #define INT2_THS_THS0 BIT_0
330
331 #define INT2_DURATION 0x37
332 #define INT2_DURATION_D6 BIT_6
333 #define INT2_DURATION_D5 BIT_5
334 #define INT2_DURATION_D4 BIT_4
335 #define INT2_DURATION_D3 BIT_3
336 #define INT2_DURATION_D2 BIT_2
337 #define INT2_DURATION_D1 BIT_1
338 #define INT2_DURATION_D0 BIT_0
339
340 // Click interrupt registers.
341 #define CLICK_CFG 0x38
342 #define CLICK_CFG_ZD BIT_5
343 #define CLICK_CFG_ZS BIT_4
344 #define CLICK_CFG_YD BIT_3
345 #define CLICK_CFG_YS BIT_2
346 #define CLICK_CFG_XD BIT_1
347 #define CLICK_CFG_XS BIT_0
348
349 #define CLICK_SRC 0x39
350 #define CLICK_SRC_IA BIT_6
351 #define CLICK_SRC_DCLICK BIT_5
352 #define CLICK_SRC_SCLICK BIT_4
353 #define CLICK_SRC_SIGN BIT_3
354 #define CLICK_SRC_Z BIT_2
355 #define CLICK_SRC_Y BIT_1
356 #define CLICK_SRC_X BIT_0
357
358 #define CLICK_THS 0x3A
359 #define CLICK_THS_LIR_CLICK BIT_7
360 #define CLICK_THS_THS6 BIT_6
361 #define CLICK_THS_THS5 BIT_5
362 #define CLICK_THS_THS4 BIT_4
363 #define CLICK_THS_THS3 BIT_3
364 #define CLICK_THS_THS2 BIT_2
365 #define CLICK_THS_THS1 BIT_1
366 #define CLICK_THS_THS0 BIT_0
367
368 #define TIME_LIMIT 0x3B
369 #define TIME_LATENCY 0x3C
370 #define TIME_WINDOW 0x3D
371 #define ACT_THS 0x3E
372 #define ACT_DUR 0x3F
373
374 #endif /* __DRV_ACC_LIS3DH_TYPES_H__ */
375
HPFilterMode_t
HPFilterMode_t
High-pass filter modes.
Definition: drv_acc_lis3dh_types.h:125
FULLSCALE_2
2 G full scale.
Definition: drv_acc_lis3dh_types.h:80
HPNormalRes
Normal mode, reference register reset when read.
Definition: drv_acc_lis3dh_types.h:127
IntOR
Sources are ORed.
Definition: drv_acc_lis3dh_types.h:99
AXISenable_t
AXISenable_t
Axis selection.
Definition: drv_acc_lis3dh_types.h:88
ODR_25Hz
High resolution/normal/low power mode 25 Hz.
Definition: drv_acc_lis3dh_types.h:58
POWER_DOWN
Acclerometer powered down.
Definition: drv_acc_lis3dh_types.h:71
ODR_10Hz
High resolution/normal/low power mode 10 Hz.
Definition: drv_acc_lis3dh_types.h:57
Int4DPos
4 direction position interrupt.
Definition: drv_acc_lis3dh_types.h:104
ODR_t
ODR_t
Output Data Rates (ODR).
Definition: drv_acc_lis3dh_types.h:54
ODR_1Hz
High resolution/normal/low power mode 1 Hz.
Definition: drv_acc_lis3dh_types.h:56
HPNormal
Normal mode.
Definition: drv_acc_lis3dh_types.h:129
IntPolarity_t
IntPolarity_t
Interrupt pin polarity.
Definition: drv_acc_lis3dh_types.h:109
Y_ENABLE
Y axis enabled.
Definition: drv_acc_lis3dh_types.h:91
IntMode_t
IntMode_t
Interrupt modes.
Definition: drv_acc_lis3dh_types.h:97
Int6DPos
6 direction position change interrupt.
Definition: drv_acc_lis3dh_types.h:102
IntAND
Sources are ANDed.
Definition: drv_acc_lis3dh_types.h:101
IntActiveLow
Active low interrupt.
Definition: drv_acc_lis3dh_types.h:112
LOW_POWER
Low power mode.
Definition: drv_acc_lis3dh_types.h:72
ODR_100Hz
High resolution/normal/low power mode 100 Hz.
Definition: drv_acc_lis3dh_types.h:60
ClickSingle
Single-click interrupt.
Definition: drv_acc_lis3dh_types.h:119
HPReference
Reference mode.
Definition: drv_acc_lis3dh_types.h:128
ODR_50Hz
High resolution/normal/low power mode 50 Hz.
Definition: drv_acc_lis3dh_types.h:59
FULLSCALE_4
4 G full scale.
Definition: drv_acc_lis3dh_types.h:81
FULLSCALE_8
8 G full scale.
Definition: drv_acc_lis3dh_types.h:82
Z_ENABLE
Z axis enabled.
Definition: drv_acc_lis3dh_types.h:92
X_ENABLE
X axis enabled.
Definition: drv_acc_lis3dh_types.h:90
ODR_400Hz
High resolution/normal/low power mode 400 Hz.
Definition: drv_acc_lis3dh_types.h:62
Int4DMov
4 direction movement interrupt.
Definition: drv_acc_lis3dh_types.h:103
ODR_1344Hz_NP_5367HZ_LP
High resolution/normal mode 1344 Hz, low power mode 5376 Hz.
Definition: drv_acc_lis3dh_types.h:64
ClickDouble
Double-click interrupt.
Definition: drv_acc_lis3dh_types.h:120
HPAutoResInt
Autoreset upon interrupt.
Definition: drv_acc_lis3dh_types.h:130
Mode_t
Mode_t
Operation modes.
Definition: drv_acc_lis3dh_types.h:69
Int6DMov
6 direction movement interrupt.
Definition: drv_acc_lis3dh_types.h:100
NORMAL
Normal mode.
Definition: drv_acc_lis3dh_types.h:73
FULLSCALE_16
16 G full scale.
Definition: drv_acc_lis3dh_types.h:83
AccAxesRaw_t
Acceleration data struct.
Definition: drv_acc_lis3dh_types.h:135
Fullscale_t
Fullscale_t
Acceleration ranges.
Definition: drv_acc_lis3dh_types.h:78
ODR_1620Hz_LP
Low power mode, 1620 Hz.
Definition: drv_acc_lis3dh_types.h:63
ODR_200Hz
High resolution/normal/low power mode 200 Hz.
Definition: drv_acc_lis3dh_types.h:61
ClickMode_t
ClickMode_t
Click interrupt modes.
Definition: drv_acc_lis3dh_types.h:117
IntActiveHigh
Active hight interrupt.
Definition: drv_acc_lis3dh_types.h:111