General Description

Functions
uint32_t	Cy_SysCM55GetStatus (MXCM55_Type *CM55Base)
	Returns the Cortex-M55 core power mode. More...

void	Cy_SysCM55Enable (MXCM55_Type *CM55Base, uint32_t vectorTableOffset, cy_app_cpu_dbg_port_type_t dbgMode, uint32_t waitus)
	Sets vector table base address and enables the Cortex-M55 core and its debug port policy. More...

void	Cy_SysCM55Disable (void)
	Disables CM55. More...

void	Cy_SysCM55Reset (MXCM55_Type *CM55Base, uint32_t waitus)
	Resets the Cortex-M55 core and waits for the mode to take the effect. More...

void	Cy_SysEnableSOCMEM (bool enable)
	Enables SOCMEM IP. More...

void	Cy_System_EnablePD1 (void)
	Safely Enables the PD1 Power Domain. More...

void	Cy_System_DisablePD1 (void)
	Safely Disables the PD1 Power Domain.

void	Cy_SysCM55SetDbgPort (cy_app_cpu_dbg_port_type_t dbgMode)
	Set APPCPU debug port mode policy. More...

void	Cy_SysU55Enable (bool enable)
	This function enables or disables the U55 ML accelerator When enabling, this enables the clock, configures the PPU to active, and sets PDCM dependency to keep the U55 active as long as the current CPU is active. More...

Function Documentation

◆ Cy_SysCM55GetStatus()

uint32_t Cy_SysCM55GetStatus ( MXCM55_Type * CM55Base )

Returns the Cortex-M55 core power mode.

Parameters

CM55Base MXCM55 base address

Returns: Core Status Macros

◆ Cy_SysCM55Enable()

void Cy_SysCM55Enable	(	MXCM55_Type *	CM55Base,
		uint32_t	vectorTableOffset,
		cy_app_cpu_dbg_port_type_t	dbgMode,
		uint32_t	waitus
	)

Sets vector table base address and enables the Cortex-M55 core and its debug port policy.

Note: If the CPU is already enabled, it is reset and then enabled.; APP_MMIO_TCM IP should be enabled before call of this API

Parameters

CM55Base	MXCM55 base address
vectorTableOffset	The offset of the vector table base address from memory address 0x00000000. The offset should be multiple to 1024 bytes.
dbgMode	debug port policy.
waitus	The timeout value in microsecond used to wait for core to be booted. value zero is for infinite wait till the core is booted successfully.

Note: : For the PSE84 device, this functions clears the first 16 words in the default vector address (for PSE84 device it is ITCM memory). The processor reads the first two words at the default vector table address to get Stack pointer and Secure reset vector address. Because the processor branches to the address read from this reset vector, this operation may causes access violation exception.

◆ Cy_SysCM55Disable()

void Cy_SysCM55Disable ( void )

Disables CM55.

Note

Below is the sequence that needs to be followed

Turn OFF the APPCPU PPU.
Enter DS on CM55.

◆ Cy_SysCM55Reset()

void Cy_SysCM55Reset	(	MXCM55_Type *	CM55Base,
		uint32_t	waitus
	)

Resets the Cortex-M55 core and waits for the mode to take the effect.

Parameters

CM55Base	MXCM55 base address
waitus	The timeout value in microsecond used to wait for core to be reset. value zero is for infinite wait till the core is reset successfully.

Warning: Do not call the function while the Cortex-M55 is executing because such a call may corrupt/abort a pending bus-transaction by the CPU and cause unexpected behavior in the system including a deadlock. Call the function while the Cortex-M55 core is in the Sleep or Deep Sleep low-power mode. Use the Power Management (syspm) API to put the CPU into the low-power modes. Use the Cy_SysPm_ReadStatus() to get a status of the CPU.

◆ Cy_SysEnableSOCMEM()

void Cy_SysEnableSOCMEM ( bool enable )

Enables SOCMEM IP.

Parameters

enable Enable or disable SOCMEM

◆ Cy_System_EnablePD1()

void Cy_System_EnablePD1 ( void )

Safely Enables the PD1 Power Domain.

This function implements the sequence required to safely enable PD1 power domain, which includes

Enabling the required CLK_HF's
Enabling/Disabling the required Power Domain Dependencies
Configuring the Power Domain PPU's with appropriate configuration
Making sure the PD's are properly enabled using the required delay's

As an illustration on when to call this function , refer to below PDCM(Power Dependency Control Matrix)...

Where the table indicates the default PDCM dependencies.

With respect to PD1, table indicates below constraints

1) If APPCPU, SOCMEM and U55 are ON then APPSS needs to be ON.

2) If APPSS is ON then PD1 needs to be ON.

If any of the APPCPU, SOCMEM, U55 and APPSS power domains need to be switched ON, user needs to call this API first to switch ON PD1 safely.

Note

Enabling peripherals in SYS_MMIO groups i.e. PERI0 group requires PD0 power domain to be ON.
Enabling peripherals in APP_MMIO groups i.e. PERI1 group requires PD1 power domain to be ON.

Once PD1 is enabled, switching ON/OFF of individual power domains under PD1 can be done using below API's

Cy_SysEnableSOCMEM

Cy_SysCM55Enable

Cy_SysU55Enable

◆ Cy_SysCM55SetDbgPort()

void Cy_SysCM55SetDbgPort ( cy_app_cpu_dbg_port_type_t dbgMode )

Set APPCPU debug port mode policy.

Parameters

dbgMode debug port policy

Disable debug port for CM55

Enables invasive debug CM55

Enables all trace and non-invasive debug features

Enables invasive debug & all trace and non-invasive enable for CM55

Invalid value passed

◆ Cy_SysU55Enable()

void Cy_SysU55Enable ( bool enable )

This function enables or disables the U55 ML accelerator When enabling, this enables the clock, configures the PPU to active, and sets PDCM dependency to keep the U55 active as long as the current CPU is active.

In Disable case it configures the PPU to off, clears the PDCM dependency to allow the U55 to disable, then disables the clock once the U55 has successfully powered off. This function waits to return until the U55 has powered off.

Parameters

enable Enable or disable U55

General Description

Functions

Function Documentation

◆ Cy_SysCM55GetStatus()

◆ Cy_SysCM55Enable()

◆ Cy_SysCM55Disable()

◆ Cy_SysCM55Reset()

◆ Cy_SysEnableSOCMEM()

◆ Cy_System_EnablePD1()

◆ Cy_SysCM55SetDbgPort()

◆ Cy_SysU55Enable()