Static Timing Analysis

Project : CyWordClock_v11
Build Time : 12/13/17 09:28:06
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 5.00
VDDA_CTB : 5.00
VDDD_0 : 5.00
VDDIO_0 : 5.00
VDDIO_1 : 5.00
VDDIO_2 : 5.00
VDDR_BGLS : 5.00
VDDR_HF : 5.00
VDDR_HLS : 5.00
VDDR_LF : 5.00
VDDR_SYN : 5.00
Voltage : 5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_intClock(FFB) ADC_intClock(FFB) 1.412 MHz 1.412 MHz N/A
CapSense_SampleClk(FFB) CapSense_SampleClk(FFB) 94.118 kHz 94.118 kHz N/A
CapSense_SenseClk(FFB) CapSense_SenseClk(FFB) 94.118 kHz 94.118 kHz N/A
Clock_1(FFB) Clock_1(FFB) 32.000 kHz 32.000 kHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 55.642 MHz
CapSense_SampleClk CyHFCLK 94.118 kHz 94.118 kHz N/A
CapSense_SenseClk CyHFCLK 94.118 kHz 94.118 kHz N/A
ADC_intClock CyHFCLK 1.412 MHz 1.412 MHz N/A
Uart_IntClock CyHFCLK 923.077 kHz 923.077 kHz 46.468 MHz
Clock_1 CyHFCLK 32.000 kHz 32.000 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:pwm8:u0\/cs_addr_0 55.642 MHz 17.972 23.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 3.850
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:pwm8:u0\/cs_addr_0 2.602
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ SETUP 11.520
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 57.448 MHz 17.407 24.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 7.340
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 6.557
macrocell12 U(1,0) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 57.448 MHz 17.407 24.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 7.340
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 6.557
macrocell13 U(1,0) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 63.203 MHz 15.822 25.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 7.340
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 4.972
macrocell18 U(1,1) 1 \StripLights:B_WS2811:pwmCntl\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwm8:u0\/cs_addr_1 65.130 MHz 15.354 26.313
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/clock_0 \StripLights:B_WS2811:pwmCntl\/q 1.250
Route 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwm8:u0\/cs_addr_1 2.584
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ SETUP 11.520
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/cl0_comb \StripLights:Net_64\/main_0 87.116 MHz 11.479 30.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/cl0_comb 5.680
Route 1 \StripLights:B_WS2811:zeroCmp\ \StripLights:B_WS2811:pwm8:u0\/cl0_comb \StripLights:Net_64\/main_0 2.289
macrocell9 U(1,1) 1 \StripLights:Net_64\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/so_comb \StripLights:Net_64\/main_4 91.726 MHz 10.902 30.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/clock \StripLights:B_WS2811:dshifter:u0\/so_comb 4.550
Route 1 \StripLights:B_WS2811:shiftOut\ \StripLights:B_WS2811:dshifter:u0\/so_comb \StripLights:Net_64\/main_4 2.842
macrocell9 U(1,1) 1 \StripLights:Net_64\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_2\/main_0 91.752 MHz 10.899 30.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 3.850
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_2\/main_0 3.539
macrocell11 U(1,0) 1 \StripLights:B_WS2811:bitCount_2\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_1\/main_0 91.752 MHz 10.899 30.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 3.850
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_1\/main_0 3.539
macrocell12 U(1,0) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_0\/main_0 91.752 MHz 10.899 30.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 3.850
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_0\/main_0 3.539
macrocell13 U(1,0) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Uart:BUART:tx_state_1\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.468 MHz 21.520 1061.813
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \Uart:BUART:tx_state_1\ \Uart:BUART:tx_state_1\/clock_0 \Uart:BUART:tx_state_1\/q 1.250
Route 1 \Uart:BUART:tx_state_1\ \Uart:BUART:tx_state_1\/q \Uart:BUART:counter_load_not\/main_0 3.098
macrocell5 U(0,1) 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/main_0 \Uart:BUART:counter_load_not\/q 3.350
Route 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\Uart:BUART:tx_state_0\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.494 MHz 21.508 1061.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/clock_0 \Uart:BUART:tx_state_0\/q 1.250
Route 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/q \Uart:BUART:counter_load_not\/main_1 3.086
macrocell5 U(0,1) 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/main_1 \Uart:BUART:counter_load_not\/q 3.350
Route 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\Uart:BUART:tx_state_2\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.760 MHz 21.386 1061.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/clock_0 \Uart:BUART:tx_state_2\/q 1.250
Route 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/q \Uart:BUART:counter_load_not\/main_3 2.964
macrocell5 U(0,1) 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/main_3 \Uart:BUART:counter_load_not\/q 3.350
Route 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.436 MHz 21.081 1062.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \Uart:BUART:tx_bitclk_enable_pre\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:counter_load_not\/main_2 2.909
macrocell5 U(0,1) 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/main_2 \Uart:BUART:counter_load_not\/q 3.350
Route 1 \Uart:BUART:counter_load_not\ \Uart:BUART:counter_load_not\/q \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \Uart:BUART:sTX:TxSts\/status_0 58.720 MHz 17.030 1066.303
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Uart:BUART:sTX:TxShifter:u0\ \Uart:BUART:sTX:TxShifter:u0\/clock \Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \Uart:BUART:tx_fifo_empty\ \Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \Uart:BUART:tx_status_0\/main_3 3.956
macrocell6 U(0,1) 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/main_3 \Uart:BUART:tx_status_0\/q 3.350
Route 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/q \Uart:BUART:sTX:TxSts\/status_0 2.874
statusicell1 U(0,0) 1 \Uart:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\Uart:BUART:sTX:TxShifter:u0\/so_comb \Uart:BUART:txn\/main_3 73.448 MHz 13.615 1069.718
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Uart:BUART:sTX:TxShifter:u0\ \Uart:BUART:sTX:TxShifter:u0\/clock \Uart:BUART:sTX:TxShifter:u0\/so_comb 7.280
Route 1 \Uart:BUART:tx_shift_out\ \Uart:BUART:sTX:TxShifter:u0\/so_comb \Uart:BUART:txn\/main_3 2.825
macrocell19 U(0,1) 1 \Uart:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \Uart:BUART:tx_state_0\/main_3 78.456 MHz 12.746 1070.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \Uart:BUART:sTX:TxShifter:u0\ \Uart:BUART:sTX:TxShifter:u0\/clock \Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \Uart:BUART:tx_fifo_empty\ \Uart:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \Uart:BUART:tx_state_0\/main_3 3.956
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\Uart:BUART:tx_state_1\/q \Uart:BUART:sTX:TxSts\/status_0 82.359 MHz 12.142 1071.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,1) 1 \Uart:BUART:tx_state_1\ \Uart:BUART:tx_state_1\/clock_0 \Uart:BUART:tx_state_1\/q 1.250
Route 1 \Uart:BUART:tx_state_1\ \Uart:BUART:tx_state_1\/q \Uart:BUART:tx_status_0\/main_0 3.098
macrocell6 U(0,1) 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/main_0 \Uart:BUART:tx_status_0\/q 3.350
Route 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/q \Uart:BUART:sTX:TxSts\/status_0 2.874
statusicell1 U(0,0) 1 \Uart:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\Uart:BUART:tx_state_0\/q \Uart:BUART:sTX:TxSts\/status_0 82.440 MHz 12.130 1071.203
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/clock_0 \Uart:BUART:tx_state_0\/q 1.250
Route 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/q \Uart:BUART:tx_status_0\/main_1 3.086
macrocell6 U(0,1) 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/main_1 \Uart:BUART:tx_status_0\/q 3.350
Route 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/q \Uart:BUART:sTX:TxSts\/status_0 2.874
statusicell1 U(0,0) 1 \Uart:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\Uart:BUART:tx_state_2\/q \Uart:BUART:sTX:TxSts\/status_0 83.278 MHz 12.008 1071.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/clock_0 \Uart:BUART:tx_state_2\/q 1.250
Route 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/q \Uart:BUART:tx_status_0\/main_4 2.964
macrocell6 U(0,1) 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/main_4 \Uart:BUART:tx_status_0\/q 3.350
Route 1 \Uart:BUART:tx_status_0\ \Uart:BUART:tx_status_0\/q \Uart:BUART:sTX:TxSts\/status_0 2.874
statusicell1 U(0,0) 1 \Uart:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\StripLights:B_WS2811:dpAddr_0\/q \StripLights:B_WS2811:dpAddr_0\/main_2 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \StripLights:B_WS2811:dpAddr_0\ \StripLights:B_WS2811:dpAddr_0\/clock_0 \StripLights:B_WS2811:dpAddr_0\/q 1.250
macrocell17 U(1,1) 1 \StripLights:B_WS2811:dpAddr_0\ \StripLights:B_WS2811:dpAddr_0\/q \StripLights:B_WS2811:dpAddr_0\/main_2 2.290
macrocell17 U(1,1) 1 \StripLights:B_WS2811:dpAddr_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dpAddr_1\/main_6 3.769
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,0) 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/clock_0 \StripLights:B_WS2811:dpAddr_1\/q 1.250
macrocell16 U(1,0) 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dpAddr_1\/main_6 2.519
macrocell16 U(1,0) 1 \StripLights:B_WS2811:dpAddr_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:bitCount_2\/main_4 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/clock_0 \StripLights:B_WS2811:bitCount_1\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:bitCount_2\/main_4 2.522
macrocell11 U(1,0) 1 \StripLights:B_WS2811:bitCount_2\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:state_1\/main_7 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/clock_0 \StripLights:B_WS2811:bitCount_1\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:state_1\/main_7 2.522
macrocell12 U(1,0) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:state_0\/main_7 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/clock_0 \StripLights:B_WS2811:bitCount_1\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_1\ \StripLights:B_WS2811:bitCount_1\/q \StripLights:B_WS2811:state_0\/main_7 2.522
macrocell13 U(1,0) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_2\/main_5 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_2\/main_5 2.522
macrocell11 U(1,0) 1 \StripLights:B_WS2811:bitCount_2\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_1\/main_8 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_1\/main_8 2.522
macrocell12 U(1,0) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_0\/main_8 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_0\/main_8 2.522
macrocell13 U(1,0) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_1\/main_4 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_1\/main_4 2.522
macrocell14 U(1,0) 1 \StripLights:B_WS2811:bitCount_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_0\/main_3 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_0\/main_3 2.522
macrocell15 U(1,0) 1 \StripLights:B_WS2811:bitCount_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:tx_state_1\/main_4 3.631
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \Uart:BUART:tx_counter_dp\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:tx_state_1\/main_4 2.631
macrocell20 U(1,1) 1 \Uart:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:tx_state_2\/main_4 3.631
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \Uart:BUART:tx_counter_dp\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:tx_state_2\/main_4 2.631
macrocell22 U(1,1) 1 \Uart:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:txn\/main_5 3.634
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \Uart:BUART:tx_counter_dp\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \Uart:BUART:txn\/main_5 2.634
macrocell19 U(0,1) 1 \Uart:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:txn\/q \Uart:BUART:txn\/main_0 3.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \Uart:BUART:txn\ \Uart:BUART:txn\/clock_0 \Uart:BUART:txn\/q 1.250
macrocell19 U(0,1) 1 \Uart:BUART:txn\ \Uart:BUART:txn\/q \Uart:BUART:txn\/main_0 2.578
macrocell19 U(0,1) 1 \Uart:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_0\/main_2 3.909
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \Uart:BUART:tx_bitclk_enable_pre\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_0\/main_2 2.909
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_1\/main_2 3.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \Uart:BUART:tx_bitclk_enable_pre\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_1\/main_2 2.928
macrocell20 U(1,1) 1 \Uart:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_2\/main_2 3.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \Uart:BUART:tx_bitclk_enable_pre\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_state_2\/main_2 2.928
macrocell22 U(1,1) 1 \Uart:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_bitclk\/main_2 3.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \Uart:BUART:tx_bitclk_enable_pre\ \Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Uart:BUART:tx_bitclk\/main_2 2.928
macrocell23 U(1,1) 1 \Uart:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:tx_state_0\/q \Uart:BUART:txn\/main_2 4.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/clock_0 \Uart:BUART:tx_state_0\/q 1.250
Route 1 \Uart:BUART:tx_state_0\ \Uart:BUART:tx_state_0\/q \Uart:BUART:txn\/main_2 2.948
macrocell19 U(0,1) 1 \Uart:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\Uart:BUART:tx_state_2\/q \Uart:BUART:tx_state_0\/main_4 4.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/clock_0 \Uart:BUART:tx_state_2\/q 1.250
Route 1 \Uart:BUART:tx_state_2\ \Uart:BUART:tx_state_2\/q \Uart:BUART:tx_state_0\/main_4 2.964
macrocell21 U(0,1) 1 \Uart:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1(FFB)
Source Destination Delay (ns)
\PWM_Alarm:cy_m0s8_tcpwm_1\/line_compl Sound_1(0)_PAD 16.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM_Alarm:cy_m0s8_tcpwm_1\ \PWM_Alarm:cy_m0s8_tcpwm_1\/clock \PWM_Alarm:cy_m0s8_tcpwm_1\/line_compl 0.000
Route 1 Net_663 \PWM_Alarm:cy_m0s8_tcpwm_1\/line_compl Sound_1(0)/pin_input 1.000
iocell3 P0[1] 1 Sound_1(0) Sound_1(0)/pin_input Sound_1(0)/pad_out 15.126
Route 1 Sound_1(0)_PAD Sound_1(0)/pad_out Sound_1(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_Alarm:cy_m0s8_tcpwm_1\/line Sound(0)_PAD 16.095
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM_Alarm:cy_m0s8_tcpwm_1\ \PWM_Alarm:cy_m0s8_tcpwm_1\/clock \PWM_Alarm:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_580 \PWM_Alarm:cy_m0s8_tcpwm_1\/line Sound(0)/pin_input 1.000
iocell2 P0[0] 1 Sound(0) Sound(0)/pin_input Sound(0)/pad_out 15.095
Route 1 Sound(0)_PAD Sound(0)/pad_out Sound(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\StripLights:StringSel:Sync:ctrl_reg\/control_0 LED_WS2812_in(0)_PAD 28.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \StripLights:StringSel:Sync:ctrl_reg\ \StripLights:StringSel:Sync:ctrl_reg\/busclk \StripLights:StringSel:Sync:ctrl_reg\/control_0 2.580
Route 1 \StripLights:saddr_0\ \StripLights:StringSel:Sync:ctrl_reg\/control_0 Net_916/main_3 2.345
macrocell1 U(1,1) 1 Net_916 Net_916/main_3 Net_916/q 3.350
Route 1 Net_916 Net_916/q LED_WS2812_in(0)/pin_input 6.083
iocell1 P1[1] 1 LED_WS2812_in(0) LED_WS2812_in(0)/pin_input LED_WS2812_in(0)/pad_out 14.005
Route 1 LED_WS2812_in(0)_PAD LED_WS2812_in(0)/pad_out LED_WS2812_in(0)_PAD 0.000
Clock Clock path delay 0.000
+ Uart_IntClock
Source Destination Delay (ns)
\Uart:BUART:txn\/q UART_TX(0)_PAD 26.982
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \Uart:BUART:txn\ \Uart:BUART:txn\/clock_0 \Uart:BUART:txn\/q 1.250
Route 1 \Uart:BUART:txn\ \Uart:BUART:txn\/q Net_190/main_0 2.583
macrocell4 U(0,1) 1 Net_190 Net_190/main_0 Net_190/q 3.350
Route 1 Net_190 Net_190/q UART_TX(0)/pin_input 5.740
iocell7 P1[5] 1 UART_TX(0) UART_TX(0)/pin_input UART_TX(0)/pad_out 14.059
Route 1 UART_TX(0)_PAD UART_TX(0)/pad_out UART_TX(0)_PAD 0.000
Clock Clock path delay 0.000