Static Timing Analysis

Project : emFile_Ble
Build Time : 02/05/18 18:17:29
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
emFile_UDB_SPI_clk_1 CyHFCLK 12.000 MHz 12.000 MHz 42.709 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 42.709 MHz 23.414 59.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/clock \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_3 5.432
macrocell1 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_3 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 2.822
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 42.772 MHz 23.380 59.953
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/clock \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_3 5.916
macrocell7 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_3 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 2.304
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \emFile_UDB_SPI_0:BSPIM:RxStsReg\/status_6 57.376 MHz 17.429 65.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/clock \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \emFile_UDB_SPI_0:BSPIM:rx_status_4\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \emFile_UDB_SPI_0:BSPIM:rx_status_6\/main_5 4.353
macrocell6 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:rx_status_6\ \emFile_UDB_SPI_0:BSPIM:rx_status_6\/main_5 \emFile_UDB_SPI_0:BSPIM:rx_status_6\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:rx_status_6\ \emFile_UDB_SPI_0:BSPIM:rx_status_6\/q \emFile_UDB_SPI_0:BSPIM:RxStsReg\/status_6 2.876
statusicell2 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_3 61.736 MHz 16.198 67.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/clock \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_3 4.388
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/main_0 61.736 MHz 16.198 67.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/clock \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp\ \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/so_comb \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/main_0 4.388
macrocell16 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:state_0\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 62.929 MHz 15.891 67.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:state_0\ \emFile_UDB_SPI_0:BSPIM:state_0\/clock_0 \emFile_UDB_SPI_0:BSPIM:state_0\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:state_0\ \emFile_UDB_SPI_0:BSPIM:state_0\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_2 4.959
macrocell1 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_2 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 2.822
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:state_2\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 64.754 MHz 15.443 67.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:state_2\ \emFile_UDB_SPI_0:BSPIM:state_2\/clock_0 \emFile_UDB_SPI_0:BSPIM:state_2\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:state_2\ \emFile_UDB_SPI_0:BSPIM:state_2\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_0 4.511
macrocell1 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/main_0 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_0 2.822
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:BitCounter\/count_0 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 65.304 MHz 15.313 68.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:BitCounter\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/clock \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_0 2.110
Route 1 \emFile_UDB_SPI_0:BSPIM:count_0\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_0 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_7 4.039
macrocell7 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_7 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 2.304
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:BitCounter\/count_2 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 65.432 MHz 15.283 68.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:BitCounter\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/clock \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_2 2.110
Route 1 \emFile_UDB_SPI_0:BSPIM:count_2\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_2 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_6 4.009
macrocell7 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_6 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 2.304
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:BitCounter\/count_4 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 65.963 MHz 15.160 68.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:BitCounter\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/clock \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_4 2.110
Route 1 \emFile_UDB_SPI_0:BSPIM:count_4\ \emFile_UDB_SPI_0:BSPIM:BitCounter\/count_4 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_4 3.886
macrocell7 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/main_4 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\ \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg_split_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\/main_1 2.304
macrocell14 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_210/q Net_210/main_3 3.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 Net_210 Net_210/clock_0 Net_210/q 1.250
macrocell12 U(1,0) 1 Net_210 Net_210/q Net_210/main_3 2.220
macrocell12 U(1,0) 1 Net_210 HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_5 3.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\ \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/clock_0 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\ \emFile_UDB_SPI_0:BSPIM:mosi_from_dp_reg\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_5 2.229
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:load_cond\/q \emFile_UDB_SPI_0:BSPIM:load_cond\/main_8 3.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:load_cond\ \emFile_UDB_SPI_0:BSPIM:load_cond\/clock_0 \emFile_UDB_SPI_0:BSPIM:load_cond\/q 1.250
macrocell15 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:load_cond\ \emFile_UDB_SPI_0:BSPIM:load_cond\/q \emFile_UDB_SPI_0:BSPIM:load_cond\/main_8 2.236
macrocell15 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:state_2\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/clock_0 \emFile_UDB_SPI_0:BSPIM:ld_ident\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:state_2\/main_9 2.601
macrocell9 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:state_0\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/clock_0 \emFile_UDB_SPI_0:BSPIM:ld_ident\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:state_0\/main_9 2.601
macrocell11 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:ld_ident\/main_8 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/clock_0 \emFile_UDB_SPI_0:BSPIM:ld_ident\/q 1.250
macrocell17 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ \emFile_UDB_SPI_0:BSPIM:ld_ident\/q \emFile_UDB_SPI_0:BSPIM:ld_ident\/main_8 2.601
macrocell17 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:cnt_enable\/q \emFile_UDB_SPI_0:BSPIM:cnt_enable\/main_3 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:cnt_enable\ \emFile_UDB_SPI_0:BSPIM:cnt_enable\/clock_0 \emFile_UDB_SPI_0:BSPIM:cnt_enable\/q 1.250
macrocell18 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:cnt_enable\ \emFile_UDB_SPI_0:BSPIM:cnt_enable\/q \emFile_UDB_SPI_0:BSPIM:cnt_enable\/main_3 2.616
macrocell18 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_4 3.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/clock_0 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/q 1.250
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_4 2.686
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:state_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_1 4.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:state_1\ \emFile_UDB_SPI_0:BSPIM:state_1\/clock_0 \emFile_UDB_SPI_0:BSPIM:state_1\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:state_1\ \emFile_UDB_SPI_0:BSPIM:state_1\/q \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\/main_1 3.141
macrocell13 U(1,0) 1 \emFile_UDB_SPI_0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile_UDB_SPI_0:BSPIM:state_1\/q \emFile_UDB_SPI_0:BSPIM:state_1\/main_1 4.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:state_1\ \emFile_UDB_SPI_0:BSPIM:state_1\/clock_0 \emFile_UDB_SPI_0:BSPIM:state_1\/q 1.250
macrocell10 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:state_1\ \emFile_UDB_SPI_0:BSPIM:state_1\/q \emFile_UDB_SPI_0:BSPIM:state_1\/main_1 3.144
macrocell10 U(0,0) 1 \emFile_UDB_SPI_0:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ emFile_UDB_SPI_clk_1
Source Destination Delay (ns)
emFile_miso_0(0)_PAD \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/route_si 23.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 emFile_miso_0(0)_PAD emFile_miso_0(0)_PAD emFile_miso_0(0)/pad_in 0.000
iocell5 P0[1] 1 emFile_miso_0(0) emFile_miso_0(0)/pad_in emFile_miso_0(0)/fb 11.538
Route 1 Net_211 emFile_miso_0(0)/fb \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\/route_si 5.506
datapathcell1 U(1,1) 1 \emFile_UDB_SPI_0:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Clock path delay 0.000
+ Clock To Output Section
+ emFile_UDB_SPI_clk_1
Source Destination Delay (ns)
\emFile_UDB_SPI_0:BSPIM:state_0\/q emFile_mosi_0(0)_PAD 30.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \emFile_UDB_SPI_0:BSPIM:state_0\ \emFile_UDB_SPI_0:BSPIM:state_0\/clock_0 \emFile_UDB_SPI_0:BSPIM:state_0\/q 1.250
Route 1 \emFile_UDB_SPI_0:BSPIM:state_0\ \emFile_UDB_SPI_0:BSPIM:state_0\/q Net_208/main_2 4.948
macrocell3 U(1,0) 1 Net_208 Net_208/main_2 Net_208/q 3.350
Route 1 Net_208 Net_208/q emFile_mosi_0(0)/pin_input 6.082
iocell4 P0[0] 1 emFile_mosi_0(0) emFile_mosi_0(0)/pin_input emFile_mosi_0(0)/pad_out 15.095
Route 1 emFile_mosi_0(0)_PAD emFile_mosi_0(0)/pad_out emFile_mosi_0(0)_PAD 0.000
Clock Clock path delay 0.000
Net_209/q emFile_sclk_0(0)_PAD 21.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,1) 1 Net_209 Net_209/clock_0 Net_209/q 1.250
Route 1 Net_209 Net_209/q emFile_sclk_0(0)/pin_input 6.198
iocell3 P0[3] 1 emFile_sclk_0(0) emFile_sclk_0(0)/pin_input emFile_sclk_0(0)/pad_out 14.526
Route 1 emFile_sclk_0(0)_PAD emFile_sclk_0(0)/pad_out emFile_sclk_0(0)_PAD 0.000
Clock Clock path delay 0.000