Static Timing Analysis

Project : CyHalloween
Build Time : 04/18/18 17:52:12
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_ModClk(FFB) CapSense_ModClk(FFB) 94.118 kHz 94.118 kHz N/A
CapSense_SnsClk(FFB) CapSense_SnsClk(FFB) 94.118 kHz 94.118 kHz N/A
Clock_1(FFB) Clock_1(FFB) 24.000 MHz 24.000 MHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 49.056 MHz
CapSense_ModClk CyHFCLK 94.118 kHz 94.118 kHz N/A
CapSense_SnsClk CyHFCLK 94.118 kHz 94.118 kHz N/A
Clock_1 CyHFCLK 24.000 MHz 24.000 MHz N/A
SPI_SCBCLK CyHFCLK 12.000 MHz 12.000 MHz N/A
UART_IntClock CyHFCLK 923.077 kHz 923.077 kHz 44.215 MHz
Clock_2 CyHFCLK 20.000 kHz 20.000 kHz 86.896 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
SPI_SCBCLK(FFB) SPI_SCBCLK(FFB) 12.000 MHz 12.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 50000ns(20 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PrISM:sC8:PrISMdp:u0\/cl0_comb Net_184/main_2 86.896 MHz 11.508 49988.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/cl0_comb 5.680
Route 1 \PrISM:cl0\ \PrISM:sC8:PrISMdp:u0\/cl0_comb Net_184/main_2 2.318
macrocell11 U(1,1) 1 Net_184 SETUP 3.510
Clock Skew 0.000
\PrISM:sC8:PrISMdp:u0\/ce0_comb Net_184/main_1 91.971 MHz 10.873 49989.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/ce0_comb 5.060
Route 1 \PrISM:ce0\ \PrISM:sC8:PrISMdp:u0\/ce0_comb Net_184/main_1 2.303
macrocell11 U(1,1) 1 Net_184 SETUP 3.510
Clock Skew 0.000
\PrISM:sC8:PrISMdp:u0\/ce1_comb Net_179/main_1 92.106 MHz 10.857 49989.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/ce1_comb 5.030
Route 1 \PrISM:ce1\ \PrISM:sC8:PrISMdp:u0\/ce1_comb Net_179/main_1 2.317
macrocell12 U(1,1) 1 Net_179 SETUP 3.510
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_1 Net_184/main_0 118.991 MHz 8.404 49991.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_1 2.580
Route 1 \PrISM:compare_type0\ \PrISM:SyncCtl:ControlReg\/control_1 Net_184/main_0 2.314
macrocell11 U(1,1) 1 Net_184 SETUP 3.510
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_2 Net_179/main_0 119.019 MHz 8.402 49991.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_2 2.580
Route 1 \PrISM:compare_type1\ \PrISM:SyncCtl:ControlReg\/control_2 Net_179/main_0 2.312
macrocell12 U(1,1) 1 Net_179 SETUP 3.510
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_0 \PrISM:enable_final_reg\/main_0 119.119 MHz 8.395 49991.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_0 2.580
Route 1 \PrISM:ctrl_enable\ \PrISM:SyncCtl:ControlReg\/control_0 \PrISM:enable_final_reg\/main_0 2.305
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ SETUP 3.510
Clock Skew 0.000
\PrISM:enable_final_reg\/q \PrISM:sC8:PrISMdp:u0\/clk_en 176.491 MHz 5.666 49994.334
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q \PrISM:sC8:PrISMdp:u0\/clk_en 2.316
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ SETUP 2.100
Clock Skew 0.000
\PrISM:enable_final_reg\/q Net_184/clk_en 176.491 MHz 5.666 49994.334
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q Net_184/clk_en 2.316
macrocell11 U(1,1) 1 Net_184 SETUP 2.100
Clock Skew 0.000
\PrISM:enable_final_reg\/q Net_179/clk_en 176.491 MHz 5.666 49994.334
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q Net_179/clk_en 2.316
macrocell12 U(1,1) 1 Net_179 SETUP 2.100
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
UARTRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 49.056 MHz 20.385 21.282
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_postpoll\/main_0 4.931
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell4 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_state_2\/main_0 73.975 MHz 13.518 28.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.961
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_state_0\/main_0 74.069 MHz 13.501 28.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_state_0\/main_0 5.944
macrocell19 U(0,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_status_3\/main_0 74.069 MHz 13.501 28.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_status_3\/main_0 5.944
macrocell27 U(0,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:pollcount_1\/main_0 79.987 MHz 12.502 29.165
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:pollcount_1\/main_0 4.945
macrocell25 U(0,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:pollcount_0\/main_0 80.077 MHz 12.488 29.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:pollcount_0\/main_0 4.931
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_last\/main_0 80.077 MHz 12.488 29.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 4.047
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_last\/main_0 4.931
macrocell28 U(0,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.215 MHz 22.617 1060.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.268
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.383 MHz 22.531 1060.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 4.182
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.169 MHz 22.139 1061.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.040
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.896 MHz 21.324 1062.009
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.975
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 54.451 MHz 18.365 1064.968
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.313
macrocell7 U(1,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.852
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 59.755 MHz 16.735 1066.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 4.273
macrocell3 U(0,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.262
statusicell1 U(0,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxSts\/status_4 60.875 MHz 16.427 1066.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,1) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:rx_status_4\/main_0 4.405
macrocell7 U(1,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_0 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.852
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 63.203 MHz 15.822 1067.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.679
macrocell5 U(0,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.323
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 63.967 MHz 15.633 1067.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 2.976
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell4 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 65.846 MHz 15.187 1068.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 2.530
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell4 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PrISM:enable_final_reg\/q \PrISM:sC8:PrISMdp:u0\/clk_en 3.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q \PrISM:sC8:PrISMdp:u0\/clk_en 2.316
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ HOLD 0.000
Clock Skew 0.000
\PrISM:enable_final_reg\/q Net_184/clk_en 3.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q Net_184/clk_en 2.316
macrocell11 U(1,1) 1 Net_184 HOLD 0.000
Clock Skew 0.000
\PrISM:enable_final_reg\/q Net_179/clk_en 3.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/clock_0 \PrISM:enable_final_reg\/q 1.250
Route 1 \PrISM:enable_final_reg\ \PrISM:enable_final_reg\/q Net_179/clk_en 2.316
macrocell12 U(1,1) 1 Net_179 HOLD 0.000
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_0 \PrISM:enable_final_reg\/main_0 4.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_0 2.040
Route 1 \PrISM:ctrl_enable\ \PrISM:SyncCtl:ControlReg\/control_0 \PrISM:enable_final_reg\/main_0 2.305
macrocell10 U(1,1) 1 \PrISM:enable_final_reg\ HOLD 0.000
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_2 Net_179/main_0 4.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_2 2.040
Route 1 \PrISM:compare_type1\ \PrISM:SyncCtl:ControlReg\/control_2 Net_179/main_0 2.312
macrocell12 U(1,1) 1 Net_179 HOLD 0.000
Clock Skew 0.000
\PrISM:SyncCtl:ControlReg\/control_1 Net_184/main_0 4.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PrISM:SyncCtl:ControlReg\ \PrISM:SyncCtl:ControlReg\/clock \PrISM:SyncCtl:ControlReg\/control_1 2.040
Route 1 \PrISM:compare_type0\ \PrISM:SyncCtl:ControlReg\/control_1 Net_184/main_0 2.314
macrocell11 U(1,1) 1 Net_184 HOLD 0.000
Clock Skew 0.000
\PrISM:sC8:PrISMdp:u0\/ce0_comb Net_184/main_1 5.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/ce0_comb 2.960
Route 1 \PrISM:ce0\ \PrISM:sC8:PrISMdp:u0\/ce0_comb Net_184/main_1 2.303
macrocell11 U(1,1) 1 Net_184 HOLD 0.000
Clock Skew 0.000
\PrISM:sC8:PrISMdp:u0\/ce1_comb Net_179/main_1 5.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/ce1_comb 3.090
Route 1 \PrISM:ce1\ \PrISM:sC8:PrISMdp:u0\/ce1_comb Net_179/main_1 2.317
macrocell12 U(1,1) 1 Net_179 HOLD 0.000
Clock Skew 0.000
\PrISM:sC8:PrISMdp:u0\/cl0_comb Net_184/main_2 5.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PrISM:sC8:PrISMdp:u0\ \PrISM:sC8:PrISMdp:u0\/clock \PrISM:sC8:PrISMdp:u0\/cl0_comb 3.130
Route 1 \PrISM:cl0\ \PrISM:sC8:PrISMdp:u0\/cl0_comb Net_184/main_2 2.318
macrocell11 U(1,1) 1 Net_184 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
UARTRX(0)/fb \UART:BUART:pollcount_0\/main_0 7.671
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:pollcount_0\/main_0 4.931
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_last\/main_0 7.671
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_last\/main_0 4.931
macrocell28 U(0,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:pollcount_1\/main_0 7.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:pollcount_1\/main_0 4.945
macrocell25 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_state_0\/main_0 8.684
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_state_0\/main_0 5.944
macrocell19 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_status_3\/main_0 8.684
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_status_3\/main_0 5.944
macrocell27 U(0,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:rx_state_2\/main_0 8.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.961
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
UARTRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 13.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P1[4] 1 UARTRX(0) UARTRX(0)/in_clock UARTRX(0)/fb 2.740
Route 1 Net_111 UARTRX(0)/fb \UART:BUART:rx_postpoll\/main_0 4.931
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell4 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.111
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,1) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.861
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.689
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.689
macrocell16 U(1,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.701
macrocell13 U(1,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.701
macrocell14 U(1,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 2.529
macrocell25 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 3.780
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 2.530
macrocell26 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell13 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.545
macrocell13 U(1,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_2\/main_5 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_2\/main_5 2.782
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_stop1_reg\/main_3 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_stop1_reg\/main_3 2.782
macrocell24 U(0,1) 1 \UART:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_4 4.036
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_4 2.786
macrocell22 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_179/q LAMP2(0)_PAD 22.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 Net_179 Net_179/clock_0 Net_179/q 1.250
Route 1 Net_179 Net_179/q LAMP2(0)/pin_input 5.918
iocell4 P3[6] 1 LAMP2(0) LAMP2(0)/pin_input LAMP2(0)/pad_out 15.420
Route 1 LAMP2(0)_PAD LAMP2(0)/pad_out LAMP2(0)_PAD 0.000
Clock Clock path delay 0.000
Net_184/q LAMP1(0)_PAD 21.748
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 Net_184 Net_184/clock_0 Net_184/q 1.250
Route 1 Net_184 Net_184/q LAMP1(0)/pin_input 5.831
iocell6 P3[7] 1 LAMP1(0) LAMP1(0)/pin_input LAMP1(0)/pad_out 14.667
Route 1 LAMP1(0)_PAD LAMP1(0)/pad_out LAMP1(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q UARTTX(0)_PAD 27.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_106/main_0 3.329
macrocell1 U(1,1) 1 Net_106 Net_106/main_0 Net_106/q 3.350
Route 1 Net_106 Net_106/q UARTTX(0)/pin_input 5.703
iocell11 P1[5] 1 UARTTX(0) UARTTX(0)/pin_input UARTTX(0)/pad_out 14.059
Route 1 UARTTX(0)_PAD UARTTX(0)/pad_out UARTTX(0)_PAD 0.000
Clock Clock path delay 0.000