Static Timing Analysis

Project : PSoC5LP_RGB_Sensor
Build Time : 05/12/18 16:02:40
Device : CY8C5888AXI-LP096
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 61.421 MHz
ADC_SAR_PD_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 50.684 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
UartRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 61.421 MHz 16.281 25.386
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_postpoll\/main_0 4.984
macrocell6 U(0,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 86.252 MHz 11.594 30.073
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 5.897
macrocell22 U(0,5) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_last\/main_0 86.252 MHz 11.594 30.073
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_last\/main_0 5.897
macrocell24 U(0,5) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 86.319 MHz 11.585 30.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 5.888
macrocell15 U(0,3) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 86.319 MHz 11.585 30.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.888
macrocell18 U(0,3) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 93.624 MHz 10.681 30.986
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 4.984
macrocell23 U(0,4) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 93.747 MHz 10.667 31.000
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 4.970
macrocell21 U(0,4) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 50.684 MHz 19.730 1063.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,5) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 6.030
macrocell2 U(1,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.910
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 51.897 MHz 19.269 1064.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,5) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 5.569
macrocell2 U(1,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.910
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.488 MHz 18.022 1065.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 5.382
macrocell2 U(1,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.910
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.597 MHz 17.362 1065.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,3) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.662
macrocell2 U(1,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.910
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 58.855 MHz 16.991 1066.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,3) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 4.715
macrocell5 U(0,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.869 MHz 15.906 1067.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 6.161
macrocell3 U(0,4) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.315
statusicell1 U(0,4) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 63.195 MHz 15.824 1067.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,4) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.548
macrocell5 U(0,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 63.219 MHz 15.818 1067.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,3) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.542
macrocell5 U(0,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 63.391 MHz 15.775 1067.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,3) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 3.499
macrocell5 U(0,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 66.181 MHz 15.110 1068.223
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,5) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 4.750
macrocell6 U(0,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 7.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 4.970
macrocell21 U(0,4) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 7.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 4.984
macrocell23 U(0,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 8.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 5.888
macrocell15 U(0,3) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 8.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.888
macrocell18 U(0,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 8.084
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 5.897
macrocell22 U(0,5) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_last\/main_0 8.084
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_last\/main_0 5.897
macrocell24 U(0,5) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 12.811
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_postpoll\/main_0 4.984
macrocell6 U(0,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,4) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.932
statusicell2 U(0,5) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.299
macrocell19 U(0,3) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.884
macrocell12 U(1,5) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_2\/main_2 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_2\/main_2 2.892
macrocell12 U(1,5) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_bitclk\/main_2 3.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_bitclk\/main_2 2.897
macrocell13 U(0,5) 1 \UART:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.095
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.905
macrocell9 U(1,5) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_1\/main_2 3.097
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_1\/main_2 2.907
macrocell10 U(0,5) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.908
macrocell10 U(0,5) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 3.419
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 2.799
macrocell15 U(0,3) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 3.419
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 2.799
macrocell18 U(0,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q UartTX(0)_PAD 28.877
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,5) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_149/main_0 2.910
macrocell1 U(1,4) 1 Net_149 Net_149/main_0 Net_149/q 3.350
Route 1 Net_149 Net_149/q UartTX(0)/pin_input 5.476
iocell1 P2[1] 1 UartTX(0) UartTX(0)/pin_input UartTX(0)/pad_out 15.891
Route 1 UartTX(0)_PAD UartTX(0)/pad_out UartTX(0)_PAD 0.000
Clock Clock path delay 0.000