\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
50.684 MHz |
19.730 |
1063.603 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell10 |
U(0,5) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:counter_load_not\/main_0 |
6.030 |
macrocell2 |
U(1,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_0 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.910 |
datapathcell2 |
U(1,5) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_2\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
51.897 MHz |
19.269 |
1064.064 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(1,5) |
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/clock_0 |
\UART:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/q |
\UART:BUART:counter_load_not\/main_3 |
5.569 |
macrocell2 |
U(1,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_3 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.910 |
datapathcell2 |
U(1,5) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
55.488 MHz |
18.022 |
1065.311 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(1,5) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:counter_load_not\/main_2 |
5.382 |
macrocell2 |
U(1,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_2 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.910 |
datapathcell2 |
U(1,5) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
57.597 MHz |
17.362 |
1065.971 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(1,3) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:counter_load_not\/main_1 |
3.662 |
macrocell2 |
U(1,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_1 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.910 |
datapathcell2 |
U(1,5) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_2\/q |
\UART:BUART:sRX:RxBitCounter\/load |
58.855 MHz |
16.991 |
1066.342 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(0,3) |
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/clock_0 |
\UART:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/q |
\UART:BUART:rx_counter_load\/main_3 |
4.715 |
macrocell5 |
U(0,3) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_3 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.316 |
count7cell |
U(0,3) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:sTX:TxSts\/status_0 |
62.869 MHz |
15.906 |
1067.427 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(1,3) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
\UART:BUART:sTX:TxShifter:u0\/clock |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART:BUART:tx_fifo_empty\ |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:tx_status_0\/main_3 |
6.161 |
macrocell3 |
U(0,4) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_3 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.315 |
statusicell1 |
U(0,4) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.195 MHz |
15.824 |
1067.509 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell14 |
U(0,4) |
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/clock_0 |
\UART:BUART:tx_ctrl_mark_last\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:rx_counter_load\/main_0 |
3.548 |
macrocell5 |
U(0,3) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_0 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.316 |
count7cell |
U(0,3) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_3\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.219 MHz |
15.818 |
1067.515 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell17 |
U(0,3) |
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/clock_0 |
\UART:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/q |
\UART:BUART:rx_counter_load\/main_2 |
3.542 |
macrocell5 |
U(0,3) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_2 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.316 |
count7cell |
U(0,3) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.391 MHz |
15.775 |
1067.558 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(0,3) |
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/clock_0 |
\UART:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/q |
\UART:BUART:rx_counter_load\/main_1 |
3.499 |
macrocell5 |
U(0,3) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_1 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.316 |
count7cell |
U(0,3) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:pollcount_0\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
66.181 MHz |
15.110 |
1068.223 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(0,5) |
1 |
\UART:BUART:pollcount_0\ |
\UART:BUART:pollcount_0\/clock_0 |
\UART:BUART:pollcount_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:pollcount_0\ |
\UART:BUART:pollcount_0\/q |
\UART:BUART:rx_postpoll\/main_2 |
4.750 |
macrocell6 |
U(0,4) |
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/main_2 |
\UART:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
2.290 |
datapathcell3 |
U(0,4) |
1 |
\UART:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|