Static Timing Analysis

Project : PSoC5LP_RGB_Sensor_Demo
Build Time : 05/12/18 16:02:15
Device : CY8C5888AXI-LP096
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
ClockBlock/dclk_glb_ff_2 ClockBlock/dclk_glb_ff_2 UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 56.319 MHz
StripLights_Clock CyMASTER_CLK 24.000 MHz 24.000 MHz 81.947 MHz
ADC_SAR_PD_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 56.319 MHz
Clock_1 CyMASTER_CLK 1.000 kHz 1.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 81.947 MHz 12.203 29.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 4.673
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 81.947 MHz 12.203 29.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 4.673
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 101.698 MHz 9.833 31.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 2.303
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_1\/main_2 102.480 MHz 9.758 31.909
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 2.050
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_1\/main_2 4.198
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_0\/main_2 102.480 MHz 9.758 31.909
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 2.050
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_0\/main_2 4.198
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_1\/main_1 117.772 MHz 8.491 33.176
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_5 2.050
Route 1 \StripLights:B_WS2811:control_5\ \StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_1\/main_1 2.931
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_0\/main_1 117.772 MHz 8.491 33.176
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_5 2.050
Route 1 \StripLights:B_WS2811:control_5\ \StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_0\/main_1 2.931
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:pwmCntl\/main_0 126.968 MHz 7.876 33.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 2.050
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:pwmCntl\/main_0 2.316
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
UartRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 56.319 MHz 17.756 23.911
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_postpoll\/main_0 6.440
macrocell6 U(1,5) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell3 U(1,5) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 82.264 MHz 12.156 29.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 6.459
macrocell26 U(1,5) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 82.393 MHz 12.137 29.530
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 6.440
macrocell19 U(1,5) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 82.501 MHz 12.121 29.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 6.424
macrocell25 U(0,3) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_last\/main_0 89.095 MHz 11.224 30.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_last\/main_0 5.527
macrocell28 U(1,4) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 91.525 MHz 10.926 30.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.229
macrocell22 U(1,4) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 91.525 MHz 10.926 30.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 5.229
macrocell27 U(1,4) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:pwm8:u0\/cs_addr_0 93.906 MHz 10.649 31.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:pwm8:u0\/cs_addr_0 2.299
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ SETUP 6.060
Clock Skew 0.000
\StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwm8:u0\/cs_addr_1 94.958 MHz 10.531 31.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/clock_0 \StripLights:B_WS2811:pwmCntl\/q 1.250
Route 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwm8:u0\/cs_addr_1 3.221
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ SETUP 6.060
Clock Skew 0.000
\StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dshifter:u0\/cs_addr_1 95.347 MHz 10.488 31.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/clock_0 \StripLights:B_WS2811:dpAddr_1\/q 1.250
Route 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dshifter:u0\/cs_addr_1 3.228
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ SETUP 6.010
Clock Skew 0.000
\StripLights:B_WS2811:state_1\/q \StripLights:B_WS2811:pwmCntl\/main_2 96.768 MHz 10.334 31.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ \StripLights:B_WS2811:state_1\/clock_0 \StripLights:B_WS2811:state_1\/q 1.250
Route 1 \StripLights:B_WS2811:state_1\ \StripLights:B_WS2811:state_1\/q \StripLights:B_WS2811:pwmCntl\/main_2 5.574
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_2\/main_0 100.492 MHz 9.951 31.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_2\/main_0 4.151
macrocell31 U(1,2) 1 \StripLights:B_WS2811:bitCount_2\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_1\/main_0 100.492 MHz 9.951 31.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_1\/main_0 4.151
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_0\/main_0 100.492 MHz 9.951 31.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:state_0\/main_0 4.151
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_1\/main_0 100.644 MHz 9.936 31.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_1\/main_0 4.136
macrocell34 U(1,2) 1 \StripLights:B_WS2811:bitCount_1\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_0\/main_0 100.644 MHz 9.936 31.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:bitCount_0\/main_0 4.136
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ SETUP 3.510
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:dpAddr_1\/main_0 100.644 MHz 9.936 31.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/z0_comb 2.290
Route 1 \StripLights:B_WS2811:pwmTC\ \StripLights:B_WS2811:pwm8:u0\/z0_comb \StripLights:B_WS2811:dpAddr_1\/main_0 4.136
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.516 MHz 17.694 1065.639
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,3) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.602
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 59.970 MHz 16.675 1066.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,4) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 4.400
macrocell5 U(1,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.368 MHz 16.565 1066.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,2) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.473
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 62.621 MHz 15.969 1067.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,5) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 3.694
macrocell5 U(1,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 62.676 MHz 15.955 1067.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.680
macrocell5 U(1,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 63.428 MHz 15.766 1067.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,4) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.491
macrocell5 U(1,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.747 MHz 15.687 1067.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,2) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 2.595
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 67.545 MHz 14.805 1068.528
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 2.773
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 69.013 MHz 14.490 1068.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 4.111
macrocell6 U(1,5) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell3 U(1,5) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 70.437 MHz 14.197 1069.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.292
macrocell7 U(1,5) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 4.475
statusicell2 U(1,4) 1 \UART:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:pwmCntl\/main_0 2.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 0.620
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:pwmCntl\/main_0 2.316
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_1\/main_1 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_5 0.620
Route 1 \StripLights:B_WS2811:control_5\ \StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_1\/main_1 2.931
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_0\/main_1 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_5 0.620
Route 1 \StripLights:B_WS2811:control_5\ \StripLights:B_WS2811:ctrl\/control_5 \StripLights:B_WS2811:state_0\/main_1 2.931
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_1\/main_2 4.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 0.620
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_1\/main_2 4.198
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_0\/main_2 4.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \StripLights:B_WS2811:ctrl\ \StripLights:B_WS2811:ctrl\/busclk \StripLights:B_WS2811:ctrl\/control_0 0.620
Route 1 \StripLights:B_WS2811:control_0\ \StripLights:B_WS2811:ctrl\/control_0 \StripLights:B_WS2811:state_0\/main_2 4.198
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 6.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:pwmCntl\/main_1 2.303
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 8.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_1\/main_3 4.673
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 8.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/busclk \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb 4.020
Route 1 \StripLights:B_WS2811:status_0\ \StripLights:B_WS2811:dshifter:u0\/f0_blk_stat_comb \StripLights:B_WS2811:state_0\/main_3 4.673
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 7.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_2\/main_0 5.229
macrocell22 U(1,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 7.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_status_3\/main_0 5.229
macrocell27 U(1,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_last\/main_0 7.714
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_last\/main_0 5.527
macrocell28 U(1,4) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 8.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_1\/main_0 6.424
macrocell25 U(0,3) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 8.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_state_0\/main_0 6.440
macrocell19 U(1,5) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 8.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:pollcount_0\/main_0 6.459
macrocell26 U(1,5) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
UartRX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P2[0] 1 UartRX(0) UartRX(0)/in_clock UartRX(0)/fb 2.187
Route 1 Net_154 UartRX(0)/fb \UART:BUART:rx_postpoll\/main_0 6.440
macrocell6 U(1,5) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell3 U(1,5) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\StripLights:B_WS2811:dshifter:u0\/so_comb \StripLights:Net_64\/main_4 3.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \StripLights:B_WS2811:dshifter:u0\ \StripLights:B_WS2811:dshifter:u0\/clock \StripLights:B_WS2811:dshifter:u0\/so_comb 0.800
Route 1 \StripLights:B_WS2811:shiftOut\ \StripLights:B_WS2811:dshifter:u0\/so_comb \StripLights:Net_64\/main_4 2.292
macrocell29 U(1,3) 1 \StripLights:Net_64\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwmCntl\/main_4 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/clock_0 \StripLights:B_WS2811:pwmCntl\/q 1.250
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ \StripLights:B_WS2811:pwmCntl\/q \StripLights:B_WS2811:pwmCntl\/main_4 2.300
macrocell38 U(1,3) 1 \StripLights:B_WS2811:pwmCntl\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dpAddr_1\/main_6 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/clock_0 \StripLights:B_WS2811:dpAddr_1\/q 1.250
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ \StripLights:B_WS2811:dpAddr_1\/q \StripLights:B_WS2811:dpAddr_1\/main_6 2.308
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:pwm8:u0\/cl0_comb \StripLights:Net_64\/main_0 3.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,4) 1 \StripLights:B_WS2811:pwm8:u0\ \StripLights:B_WS2811:pwm8:u0\/clock \StripLights:B_WS2811:pwm8:u0\/cl0_comb 0.780
Route 1 \StripLights:B_WS2811:zeroCmp\ \StripLights:B_WS2811:pwm8:u0\/cl0_comb \StripLights:Net_64\/main_0 2.911
macrocell29 U(1,3) 1 \StripLights:Net_64\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_2\/main_5 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_2\/main_5 2.584
macrocell31 U(1,2) 1 \StripLights:B_WS2811:bitCount_2\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_1\/main_8 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_1\/main_8 2.584
macrocell32 U(1,2) 1 \StripLights:B_WS2811:state_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_0\/main_8 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:state_0\/main_8 2.584
macrocell33 U(1,2) 1 \StripLights:B_WS2811:state_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_1\/main_4 3.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_1\/main_4 2.588
macrocell34 U(1,2) 1 \StripLights:B_WS2811:bitCount_1\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_0\/main_3 3.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:bitCount_0\/main_3 2.588
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ HOLD 0.000
Clock Skew 0.000
\StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:dpAddr_1\/main_5 3.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(1,2) 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/clock_0 \StripLights:B_WS2811:bitCount_0\/q 1.250
Route 1 \StripLights:B_WS2811:bitCount_0\ \StripLights:B_WS2811:bitCount_0\/q \StripLights:B_WS2811:dpAddr_1\/main_5 2.588
macrocell36 U(1,2) 1 \StripLights:B_WS2811:dpAddr_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(1,4) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.317
statusicell2 U(1,4) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.597
macrocell16 U(0,2) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.605
macrocell13 U(0,2) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.605
macrocell14 U(0,2) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.309
macrocell23 U(1,5) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_0\/main_2 2.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_0\/main_2 2.309
macrocell26 U(1,5) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.315
macrocell23 U(1,5) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_6 2.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_6 2.315
macrocell19 U(1,5) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.315
macrocell20 U(1,5) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 2.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 2.316
macrocell19 U(1,5) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\StripLights:StringSel:Sync:ctrl_reg\/control_3 WS2812B(0)_PAD 30.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \StripLights:StringSel:Sync:ctrl_reg\ \StripLights:StringSel:Sync:ctrl_reg\/busclk \StripLights:StringSel:Sync:ctrl_reg\/control_3 2.050
Route 1 \StripLights:saddr_3\ \StripLights:StringSel:Sync:ctrl_reg\/control_3 Net_122/main_0 2.322
macrocell9 U(0,5) 1 Net_122 Net_122/main_0 Net_122/q 3.350
Route 1 Net_122 Net_122/q WS2812B(0)/pin_input 7.337
iocell3 P0[6] 1 WS2812B(0) WS2812B(0)/pin_input WS2812B(0)/pad_out 15.561
Route 1 WS2812B(0)_PAD WS2812B(0)/pad_out WS2812B(0)_PAD 0.000
Clock Clock path delay 0.000
+ StripLights_Clock
Source Destination Delay (ns)
\StripLights:Net_64\/q WS2812B(0)_PAD 31.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,3) 1 \StripLights:Net_64\ \StripLights:Net_64\/clock_0 \StripLights:Net_64\/q 1.250
Route 1 \StripLights:Net_64\ \StripLights:Net_64\/q Net_122/main_4 3.650
macrocell9 U(0,5) 1 Net_122 Net_122/main_4 Net_122/q 3.350
Route 1 Net_122 Net_122/q WS2812B(0)/pin_input 7.337
iocell3 P0[6] 1 WS2812B(0) WS2812B(0)/pin_input WS2812B(0)/pad_out 15.561
Route 1 WS2812B(0)_PAD WS2812B(0)/pad_out WS2812B(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q UartTX(0)_PAD 30.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_149/main_0 2.797
macrocell1 U(0,2) 1 Net_149 Net_149/main_0 Net_149/q 3.350
Route 1 Net_149 Net_149/q UartTX(0)/pin_input 6.749
iocell1 P2[1] 1 UartTX(0) UartTX(0)/pin_input UartTX(0)/pad_out 15.891
Route 1 UartTX(0)_PAD UartTX(0)/pad_out UartTX(0)_PAD 0.000
Clock Clock path delay 0.000