\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
56.516 MHz |
17.694 |
1065.639 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(0,3) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:counter_load_not\/main_1 |
4.602 |
macrocell2 |
U(0,2) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_1 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.302 |
datapathcell2 |
U(0,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:sRX:RxBitCounter\/load |
59.970 MHz |
16.675 |
1066.658 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(1,4) |
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/clock_0 |
\UART:BUART:tx_ctrl_mark_last\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:rx_counter_load\/main_0 |
4.400 |
macrocell5 |
U(1,5) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_0 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.315 |
count7cell |
U(1,5) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_2\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
60.368 MHz |
16.565 |
1066.768 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell16 |
U(0,2) |
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/clock_0 |
\UART:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/q |
\UART:BUART:counter_load_not\/main_3 |
3.473 |
macrocell2 |
U(0,2) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_3 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.302 |
datapathcell2 |
U(0,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxBitCounter\/load |
62.621 MHz |
15.969 |
1067.364 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(1,5) |
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/clock_0 |
\UART:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/q |
\UART:BUART:rx_counter_load\/main_1 |
3.694 |
macrocell5 |
U(1,5) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_1 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.315 |
count7cell |
U(1,5) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_3\/q |
\UART:BUART:sRX:RxBitCounter\/load |
62.676 MHz |
15.955 |
1067.378 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(1,4) |
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/clock_0 |
\UART:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/q |
\UART:BUART:rx_counter_load\/main_2 |
3.680 |
macrocell5 |
U(1,5) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_2 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.315 |
count7cell |
U(1,5) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_2\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.428 MHz |
15.766 |
1067.567 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(1,4) |
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/clock_0 |
\UART:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/q |
\UART:BUART:rx_counter_load\/main_3 |
3.491 |
macrocell5 |
U(1,5) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_3 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.315 |
count7cell |
U(1,5) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
63.747 MHz |
15.687 |
1067.646 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell14 |
U(0,2) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:counter_load_not\/main_0 |
2.595 |
macrocell2 |
U(0,2) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_0 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.302 |
datapathcell2 |
U(0,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
67.545 MHz |
14.805 |
1068.528 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(0,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:counter_load_not\/main_2 |
2.773 |
macrocell2 |
U(0,2) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_2 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.302 |
datapathcell2 |
U(0,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:pollcount_1\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
69.013 MHz |
14.490 |
1068.843 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell25 |
U(0,3) |
1 |
\UART:BUART:pollcount_1\ |
\UART:BUART:pollcount_1\/clock_0 |
\UART:BUART:pollcount_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:pollcount_1\ |
\UART:BUART:pollcount_1\/q |
\UART:BUART:rx_postpoll\/main_1 |
4.111 |
macrocell6 |
U(1,5) |
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/main_1 |
\UART:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
2.309 |
datapathcell3 |
U(1,5) |
1 |
\UART:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:sRX:RxSts\/status_4 |
70.437 MHz |
14.197 |
1069.136 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell3 |
U(1,5) |
1 |
\UART:BUART:sRX:RxShifter:u0\ |
\UART:BUART:sRX:RxShifter:u0\/clock |
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART:BUART:rx_fifofull\ |
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:rx_status_4\/main_1 |
2.292 |
macrocell7 |
U(1,5) |
1 |
\UART:BUART:rx_status_4\ |
\UART:BUART:rx_status_4\/main_1 |
\UART:BUART:rx_status_4\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_status_4\ |
\UART:BUART:rx_status_4\/q |
\UART:BUART:sRX:RxSts\/status_4 |
4.475 |
statusicell2 |
U(1,4) |
1 |
\UART:BUART:sRX:RxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|